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European Conference on Solid-State device research (ESSdErC)

作者： d. Ha d. Shin G. Koh J. Lee S. Lee H. Jeong T. Chung K. Kim Technology Development Semiconductor R&D Center Samsung Electronics Company Limited Yongin si Kyunggi South Korea

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NILE: a novel platform-independent and efficient distributed simulation system for TCAd

NILE: a novel platform-independent and efficient distributed...

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International Conference on Simulation of Semiconductor Processes and devices (SISPAd)

作者： K. Yoshitomi T. Tatsumi N. Nakauchi M. Mukai Y. Komatsu ULSI R&D Laboratories LSI Business & Technology Development Group Core Technology & Network Company Sony Corporation Atsugi Kanagawa Japan

We have developed a Java-based novel system called NILE, which is tolerable for practical use and working on a distributed environment for semiconductor process and device simulations. NILE enables the utilization of simulation in practical use from remote sites even if the network bandwidth is narrow. NILE has succeeded in providing the same kind of simulation environment regardless of the kinds of platforms. Furthermore, NILE enables developing devices for USLI much more efficiently using the central servers.

关键词： File servers Network servers Protocols Local area networks Java Analytical models Computer networks Bandwidth Process control Production facilities

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Novel integration technology with capacitor over metal (COM) by using self-aligned dual damascene (SAdd) process for 0.15 /spl mu/m stand-alone and embedded drAMs

Novel integration technology with capacitor over metal (COM)...

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Symposium on VLSI technology

作者： Won Suk Yang Yeong Kwan Kim Soo Ho Shin Won Seok Lee Kyu Hyun Lee Hong Sik Jeong Jong Ho Lee Tae Young Chung Heung Soo Park Sang In Lee Kinam Kim Moon Yong Lee Chang Gyu Hwang Technology and Process Development Team Semiconductor R&D Center Samsung Electronics Company Limited Yongin si Gyeonggi South Korea

ISBN: (纸本)493081393X

A novel integration technology with capacitor over metal (COM) for 0.15 /spl mu/m stand-alone and embedded drAMs is developed using a self-aligned dual damascene (SAdd) process, which offers great breakthroughs. First, many back-end metallization issues encountered in conventional COB (capacitor over bit line) drAMs are simply overcome because the capacitor is formed after the metal lines. Secondly, memory cell capacitors can be integrated much more simply and easily compared to those of conventional COB technology because the memory cell contact and storage node are formed simultaneously. Furthermore, transistor performance can be greatly improved because a novel poly-Si/Al/sub 2/O/sub 3//poly-Si capacitor is integrated at temperatures below 400/spl deg/C.

关键词： Capacitors random access memory dielectrics dry etching Moon research and development Metallization Integrated circuit technology Capacitance Filling

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Environmental assessment on operating condition of the demonstration plant for recycling post-use electric home appliances

Environmental assessment on operating condition of the demon...

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International Symposium on Environmentally Conscious design and Inverse Manufacturing (Ecodesign)

作者： M. Sanou A. Fujita H. Hoshina Advanced Technology R&D Center Mitsubishi Electronic Corporation Amagasaki Hyogo Japan Energy and Ecosystem Business Division Mitsubishi Material Corporation Bunkyo Tokyo Japan

The Japanese Association for Electrical Home Appliances (AEHA) has developed an integrated recycling system for four large domestic appliances. As the member companies of the project, subsidized by Ministry of International Trade and Industry (MITI), the authors developed an artificial intelligence (AI) system to control the plant for labor reduction and automatic treatment. Environmental assessment on the operating condition of the plant can be executed through the AI system.

关键词： recycling

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A 3.6 Gb/s 340 mW 16:1 pipe-lined multiplexer using SOI-CMOS technology

A 3.6 Gb/s 340 mW 16:1 pipe-lined multiplexer using SOI-CMOS...

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Symposium on VLSI Circuits

作者： T. Nakura K. Ueda K. Kubo W. Fernandez Y. Matsuda K. Mashiko System LSI Development Center Mitsubishi Electric Corporation Limited Itami Hyogo Japan Information Technology R&D Center Mitsubishi Electric Corporation Limited Itami Hyogo Japan ULSI Development Center Mitsubishi Electric Corporation Limited Itami Hyogo Japan

This paper describes a 16:1 multiplexer (MUX) using a 0.18 /spl mu/m partially-depleted SOI-CMOS technology. Owing to a selector type architecture with a pipeline structure as well as small junction capacitances of SO... 详细信息

关键词： Multiplexing Circuits Timing Capacitance CMOS technology Pipelines Clocks delay effects Frequency Large scale integration

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Low resistance Co-salicided 0.1 /spl mu/m CMOS technology using selective Si growth

Low resistance Co-salicided 0.1 /spl mu/m CMOS technology us...

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Symposium on VLSI technology

作者： H. Sayama S. Shimizu Y. Nishida T. Kuroi Y. Kanda M. Fujisawa Y. Inoue T. Nishimura T. Oishi T. Nakahata T. Furukawa S. Yamakawa Y. Abe S. Maruno Y. Tokuda S. Satoh ULSI Dev. Center Mitsubishi Electr. Corp. Hyogo Japan ULSI Development Center Mitsubishi Electric Corporation Limited Itai Hyogo Japan Advanced Technology R&D Center Mitsubishi Electric Corporation Limited Itai Hyogo Japan

A low resistance salicided 0.1 /spl mu/m CMOSFET has been developed with precisely controlled T-shaped gate and optimum gate structure for thick CoSi/sub 2/. Selective Si growth (SSG) using a SiO/sub 2/-SiN stacked sidewall with the exposed SiN top hill enables suppression of junction leakage for thick Co silicidation, to eliminate bridging between gate and source/drain (S/d), and to precisely control the extra gate length for T-shaped gates. Moreover, the nitrogen profile in the p/sup +/ gate is optimized to suppress gate depletion induced by the thick Co. Since a heavily nitrided gate oxide insulator and N implantation of the poly-Si surface can prevent gate-implanted B ions from being diffused into the substrate and into the CoSi/sub 2/ layer, an increase in the gate sheet resistance, B penetration, and gate depletion can be simultaneously resolved, and thus high performance 0.1 /spl mu/m CMOS can be achieved with gates of as low as 1.9 /spl Omega//sq. sheet resistance.

关键词： CMOS technology Silicon compounds Insulation Surface resistance doping Paper technology Space technology Voltage Silicides Very large scale integration

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Barrier properties of Ta–ruO2 diffusion barrier for dynamic random access memory capacitor bottom electrodes

Journal of Vacuum Science & Technology B: Microelectronics a...

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Journal of Vacuum Science & technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena 1999年第4期17卷 1470-1476页

作者： dong-Soo Yoon Hong Koo Baik Sung-Man Lee Sang-In Lee Department of Metallurgical Engineering Yonsei University Seoul 120-749 Korea Department of Materials Engineering Kangwon National University Chuncheon Kangwon-Do 200-701 Korea Development of Technology Semiconductor R&D Center Samsung Electronics Co. San#24 Nongseo-Lee Kiheung-Eup Yongin-City Kyungki-Do 449-900 Korea

We proposed the Ta–ruO2 diffusion barrier for oxygen in the dynamic random access memory capacitor bottom electrode, and investigated the barrier and electrical properties of the developed diffusion barrier. The Ta–ruO2/TiSi2/poly-Si/SiO2/Si contact system deposited with and without the SiO2 capping layer showed the lower total resistance and ohmic characteristics up to 800 °C. For the Ta–ruO2/TiSi2/poly-Si/SiO2/Si contact system, no other phases observed except for the formation of conductive ruO2 phase in the barrier film by reaction with the indiffused oxygen after annealing in air, but the thin oxidized layer at the Ta–ruO2/TiSi2 interface was formed by external oxygen. However, a large number of the crystallites in the annealed samples compared to that of as-deposited film were observed even after depth profile. The crystallites consisted of ru and O containing a small amount of Ta. In addition, the embedded ruO2 crystalline phase was observed in the thin oxidized TiSi2 surface layer. Correspondingly, we suggest that the ohmic mechanism of the Ta–ruO2/TiSi2/poly-Si/SiO2/Si contact system is an embedded ruO2 crystalline phase involving a small amount of Ta in a Ta amorphous structure.

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0.1 /spl mu/m level contact hole pattern formation with KrF lithography by resolution enhancement lithography assisted by chemical shrink (rELACS)

0.1 /spl mu/m level contact hole pattern formation with KrF ...

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International Electron devices Meeting (IEdM)

作者： T. Toyoshima T. Ishibashi A. Minanide K. Sugino K. Katayama T. Shoya I. Arimoto N. Yasuda H. Adachi Y. Matsui Advanced Technology R&D Center Mitsubishi Electronic Corporation Amagasaki Hyogo Japan ULSI Development Center Mitsubishi Electronic Corporation Itami Hyogo Japan Ryoden Semiconductor System Engineering Corporation Itami Hyogo Japan

We developed a hole shrink process named rELACS (resolution Enhancement Lithography Assisted by Chemical Shrink) that is a robust and low-cost method. This method makes use of crosslinking reaction between the materials coated on the resist pattern, and the acid existing at the resist wall. By the rELACS, we could shrink KrF resist hole patterns to 0.1 /spl mu/m level. The shrinkage of hole size is dependent on both baking temperature and initial hole size. This process has been established for the fabrication of 0.20 /spl mu/m devices.

关键词： Pattern formation Lithography resists Shape Size control Temperature dependence Chemical processes

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The best combination of aluminum and copper interconnects for a high performance 0.18 /spl mu/m CMOS logic device

The best combination of aluminum and copper interconnects fo...

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International Electron devices Meeting (IEdM)

作者： M. Igarashi A. Harada H. Amishiro H. Kawashima N. Morimoto Y. Kusumi T. Saito A. Ohsaki T. Mori T. Fukada Y. Toyoda K. Higashitani H. Arima ULSI Development Center Mitsubishi Electronic Corporation Itami Hyogo Japan Mitsubishi Denki Kabushiki Kaisha Chiyoda-ku Tokyo JP Advanced Technology R&D Center Mitsubishi Electronic Corporation Amagasaki Hyogo Japan

A high performance 0.18 /spl mu/m CMOS logic device has been developed with 0.15 /spl mu/m transistors and six-level interconnects. The multi-level interconnect system consists of a conventional process with Al wire and a dual damascene process with Cu wire. 4-level Al interconnects with fine metal pitch are suitable for short distance wiring such as intra block cell to cell interconnects, whereas 2-level Cu interconnects with coarse metal pitch are used for long distance wiring such as mega block to block interconnects to achieve high-speed and high-density LSI devices.

关键词： Aluminum Copper Wire Parasitic capacitance Wiring delay effects High-K gate dielectrics Logic devices Etching Oxidation

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Investigation of Pt/Ta diffusion barrier using hybrid conductive oxide (ruO2) for high dielectric applications

Journal of Vacuum Science & Technology B: Microelectronics a...

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Journal of Vacuum Science & technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena 1998年第3期16卷 1137-1141页

作者： dong-Soo Yoon Hong Koo Baik Sung-Man Lee Sang-In Lee Hyun ryu Hwack Joo Lee Department of Metallurgical Engineering Yonsei University Seoul 120-749 Korea Department of Materials Engineering Kangwon National University Chuncheon Kangwon-Do 200-701 Korea Technology Development Semiconductor R&D Center Samsung Electronics Co. San#24 Nongseo-Lee Kiheung-Eup Yongin-City Kyungki-Do 449-900 Korea New Material Evaluation Center KRISS Taejon 305-600 Korea

The Pt/Ta diffusion barrier using hybrid conductive oxide (ruO2) for dynamic random access memory and ferroelectric random access memory capacitor bottom electrodes is proposed. The thermal stability of Pt+ruO2 (50 nm)/Ta+ruO2 (50 nm)/TiSi2/poly-Si/SiO2/Si contact system is investigated and compared to that of the Pt(50 nm)/Ta(50 nm)/TiSi2/poly-Si/SiO2/Si contact system. The Pt+ruO2/Ta+ruO2/TiSi2/poly-Si/SiO2/Si contact system sustained its structure up to 650 °C, whereas Pt/Ta/TiSi2/poly-Si/SiO2/Si contact system was completely degraded after annealing at 650 °C. In the former case, the addition of ruthenium dioxide (ruO2) into the Pt bottom electrode layer led to retardation of the oxygen indiffusion, preventing the indiffusion of oxygen up to 650 °C. In addition, the Ta+ruO2 diffusion barrier showed an amorphous structure and ruO2 is bound to the Ta matrix, inhibiting the interdiffusion of O, Pt, and Si through grain boundaries which can act as fast diffusion paths up to high temperatures. Therefore, it appeared that the barrier properties of Pt/Ta diffusion barrier are improved by using hybrid conductive oxide (ruO2).

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