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Electronic Components and technology Conference (ECTC)

作者： K. Harada S. Baba Qiang Wu H. Matsushima T. Matsunaga Y. Ucgai M. Kimura Advanced Package Development Sect. Assembly Engineering Dept. Mitsubishi Electric Corp. Itami Hyogo Japan Advanced Technology R&D Center Mitsubishi Electric Corp. Itami Hyogo Japan

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Sub-10-nm planar-bulk-CMOS devices using lateral junction control

Sub-10-nm planar-bulk-CMOS devices using lateral junction co...

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International Electron devices Meeting (IEdM)

作者： H. Wakabayashi S. Yamagami N. Ikezawa A. Ogura M. Narihiro K. Arai Y. Ochiai K. Takeuchi T. Yamamoto T. Mogami Silicon Systems Research Laboratories Sagamihara Kanagawa Japan Advanced Technology Development Division NEC Electronics Corporation Limited Sagamihara Kanagawa Japan R&D Support Center NEC Corporation Limited Sagamihara Kanagawa Japan

Sub-10-nm planar-bulk-CMOS devices were clearly demonstrated by a lateral source/drain (S/d) junction control using the precisely-controlled gate-electrode, shallow source/drain extensions (SdE) and steep halo. Good c... 详细信息

关键词： Electrodes Annealing resists MOSFET circuits Plasma temperature dielectric thin films Lithography Silicon Laboratories research and development

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Fabrication of HfSiON gate dielectrics by plasma oxidation and nitridation, optimized for 65 nm mode low power CMOS applications

Fabrication of HfSiON gate dielectrics by plasma oxidation a...

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Symposium on VLSI technology

作者： S. Inumiya K. Sekine S. Niwa A. Kaneko M. Sato T. Watanabe H. Fukui Y. Kamata M. Koyama A. Nishiyama M. Takayanagi K. Eguchi Y. Tsunashima Process and Manufacturing Engineering Center Process and Manufacturing Engineering Center Yokohama Japan SoC Research & Development Center Semiconductor Company Yokohama Japan Advanced LSI Technology Laboratory R&D Center Toshiba Corporation Isogo-ku Yokohama Japan SoC Research & Development Center Semiconductor Company

Fabrication process of HfSiON gate dielectrics by plasma oxidation of CVd Hf silicate followed by plasma nitridation was developed. Thanks to the high quality ultrathin interfacial layer formed by internal plasma oxidation, electron mobility of 240 cm/sup 2//Vs@0.8 MV/cm (85% of SiO/sub 2/) and hole mobility of 73 cm/sup 2//Vs@0.5 MV/cm (93% of SiON) were successfully achieved. The developed process will be promising for the production of low power CMOS devices in the near future.

关键词： Fabrication dielectrics Plasma applications Oxidation Hafnium Nitrogen Plasma properties Plasma materials processing Plasma stability CMOS process

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Phase-change chalcogenide nonvolatile rAM completely based on CMOS technology

Phase-change chalcogenide nonvolatile RAM completely based o...

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International Symposium on VLSI technology, Systems and Applications

作者： Y.N. Hwang J.S. Hong S.H. Lee S.J. Ahn G.T. Jeong G.H. Koh H.J. Kim W.C. Jeong S.Y. Lee J.H. Park K.C. ryoo H. Horii Y.H. Ha J.H. Yi W.Y. Cho Y.T. Kim K.H. Lee S.H. Joo S.O. Park U.I. Jeong H.S. Jeong Kinam Kim Advanced Technology Development Semiconductor R&D Division Samsung Electronics Company Limited Yongin si Kyunggi South Korea Process Development Samsung Electronics Company Limited Yongin si Kyunggi South Korea Process Development Samsung Electronics Co. Ltd Yongin Korea Computer Aided Engineering Teams Samsung Electronics Co. Ltd Yongin Korea

ISBN: (纸本)0780377656

We have integrated a phase-change chalcogenide random access memory, completely based on 0.24 /spl mu/m-CMOS technologies. A twin cell and BL clamping circuits are introduced to enlarge fabrication tolerance and to reduce cell perturbation during reading operation. To draw back current as much as possible, Co salicidation is also applied to transistor formation. By constructing a simple cell structure with Ge/sub 2/Sb/sub 2/Te/sub 5/, we have observed reliable phase-transitions by driving current through MOS transistors. With 100 ns-writing pulses of 2 mA for rESET and 0.6 mA for SET, the device operates successfully with a considerable sensing signal at reading voltage of as low as 0.2 V.

关键词： CMOS technology Integrated circuit technology Nonvolatile memory read-write memory random access memory Clamps Fabrication Tellurium MOSFETs Low voltage

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An in-parallel actuated manipulator with redundant actuators for gross and fine motions

An in-parallel actuated manipulator with redundant actuators...

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IEEE International Conference on robotics and Automation (ICrA)

作者： Y. Takeda H. Funabashi K. Ichikawa K. Hirose Department of Mechanical Sciences and Engineering Tokyo Institute of Technology Tokyo Japan Tochigi R&D Center AP Research Department Honda Research and Development Company Limited Haga Tochigi Japan Department of Mechanical Engineering Shibaura Institute of Technology Tokyo Japan Hephaist Seiko Company Limited Kawagoe Saitama Japan

We propose an in-parallel actuate mechanism that can simultaneously realize fine positioning resolution and a large working space, and we discuss its infinitesimal displacement characteristics. Based on a kinematic synthesis of this mechanism, an experimental manipulator has been developed and we discuss the results of experiments regarding its fine positioning characteristics.

关键词： Actuators Manipulators Space technology Kinematics research and development Joining processes Mechanical engineering dVd Vibrations Spatial resolution

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Nitride-based HFETs with carrier confinement layers

Nitride-based HFETs with carrier confinement layers

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International Symposium Semiconductor device research (ISdrS)

作者： S.J. Chang Y.K. Su T.M. Kuan C.H. Ko S.C. Wei W.H. Lan Y.T. Cherng S.C. Chen Institute of Microelectronics and Department of Electrical Engineering National Cheng Kung University Tainan Taiwan R.O.C Department of Electrical Engineering National University of Kaohsiung Kaohsiung Taiwan R.O.C Materials R&D Center Chung Shan Institute a/Science & Technology Taoyuan Taiwan R.O.C Department of Electronic Engineering National Yunlin University of Science and Technology Touliu Taiwan R.O.C

Nitride-based Al/sub 0.24/Ga/sub 0.76/N/GaN heterostructure field effect transistors (HFETs) with carrier confinement layers were fabricated. The results found that the enhanced 2 dimensional electron gas (2dEG) carrier mobility from 1070 to 1180 cm/sup 2/V/sup -1/sec/sup -1/ by the insertion of a Mg-doped semi-insulating carrier confinement layer with a Cp/sub 2/Mg flow rate of 2.36/spl times/10/sup -8/ mole/min and smoother sample surface. The dC and rF characteristics of these HFETs were also good.

关键词： HEMTs MOdFETs Carrier confinement research and development Gallium nitride Electron mobility radio frequency

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Nitride-based devices fabricated by wet etching

Nitride-based devices fabricated by wet etching

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International Symposium Semiconductor device research (ISdrS)

作者： S.J. Chang Y.K. Su T.M. Kuan C.H. Ko S.C. Wei W.H. Lan J.B. Webb Y.T. Cherng S.C. Chen Institute of Microelectronics and Department of Electrical Engineering National Cheng Kung University Tainan Taiwan Department ofElectrica1 Engineering National University of Kaohsiung Kaohsiung Taiwan Institutefor Microstructural Science National Research Council Canada Ottawa Canada Materials R&D Center Chung Shang Institute of Science and Technology Taoyuan Taiwan Department of EIectronic Engineering National Yunlin University of Science and Technology Tou-Liu Taiwan

Photo-enhanced chemical (PEC) wet etching technology was used to etch GaN and AlGaN epitaxial layers. Figure 1 shows PEC etch rate for the GaN and Al/sub x/Ga/sub 1-x/N epitaxial layers in aqueous KOH and H/sub 3/PO/sub 4/ solutions. It was found that the maximum etch rates were 510 nm/min, 1960 nm/min, 300 nm/min and 0 nm/min for GaN, Al/sub 0.175/Ga/sub 0.825/N, Al/sub 0.23/Ga/sub 0.77/N and Al/sub 0.4/Ga/sub 0.6/N, respectively. Nitride-based Schottky diodes and heterostructure field effect transistors (HFETs) were also fabricated by PEC wet etching. As shown in figures 2, 3 and 4, it was found that we could achieve a saturated I/sub d/ larger than 850 mA/mm and a maximum g/sub m/ about 163 mS/mm from PEC wet etched HFET with a 0.5/spl mu/m gate length. Compared with dry etched devices, the leakage currents observed from the PEC wet etched devices were also found to be smaller.

关键词： Wet etching Gallium nitride HEMTs MOdFETs Chemical technology Epitaxial layers dry etching Aluminum gallium nitride Schottky diodes Leakage current

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High efficiency amoled using hybrid of small molecule and polymer materials patterned by laser transfer

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Journal of Information display 2003年第3期4卷 1-5页

作者： Chin, Byung doo Suh, Min Chul Kim, Mu Hyun Kang, Tae Min Yang, Nam Choul Song, Myung Won Lee, Seong Taek Kwon, Jang Hyuk Chung, Ho Kyoon Wolk, Martin B. Bellmann, Erika Baetzold, John P. Corporate R&D Center Samsung SDI Co. Ltd. Yongin-City Kyungki-Do 449–577 428–5 Gongse-Ri Kiheung-Up South Korea Corporate R&D Center Samsung SDI Co. Ltd. Yongin-City Kyungki-Do 449–577 428–5 Gongse-Ri Kiheung-Up South Korea 3M Display Materials Technology Center St Paul MN 55144–1000 3M Center Building 0236 United States

Laser-Induced Thermal Imaging (LITI) is a laser addressed patterning process and has unique advantages such as high-resolution patterning with over all position accuracy of the imaged stripes of within 2.5 micrometer and scalability to large-size mother glass. This accuracy is accomplished by real-time error correction and a high-resolution stage control system that includes laser interferometers. Here the new concept of hybrid system that complement the merits of small molecule and polymer to be used as an OLEd;our system can realize easy processing of light emitting polymers and high luminance efficiency of small molecules. LITI process enables the stripes to be patlerned with excellent thickness uniformity and multi-stacking of various functional layers without having to use any type of fine metal shadow mask. In this study, we report a full-color hybrid OLEd using the multi-layered structure consisting of small molecules and polymers. © 2003 Taylor & Francis Group, LLC.

关键词： AMOLEd High efficiency Hybrid Laser-induced thermal imaging Patterning

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Improvement of NBTI and electrical characteristics by ozone pre-treatment and PBTI issues in HfAlO(N) high-k gate dielectrics

Improvement of NBTI and electrical characteristics by ozone ...

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International Electron devices Meeting (IEdM)

作者： Seok Joo doh Hyung-Suk Jung Yun-Seok Kim Ha-Jin Lim Jong Pyo Kim Jung Hyoung Lee Jong-Ho Lee Nae-In Lee Ho-Kyu Kan Kwang-Pyuk Suh Seong Geon Park Sang Bom Kang Gil Heyun Choi Young-Su Chung Hion-Suck Baikz Hdyo-Sik Chang Mann-Ho Cho dae-Won Moon Hong Bae Park Moonju Cho Cheol Seong Hwang Advanced Process Development Project System LSI Business Samsung Electronics Co. Ltd Yongin Kyunggi-Do Korea Process Development Team 2 Semiconductor R & D Center Samsung Electronics Co. Ltd South Korea AE Center Samsung Advanced Institute of Technology South Korea AE Center Samsung Advanced Institute of Technology Nano Surface group Korea Research Institute of Standard and Science South Korea Nano Surface group Korea Research Institute of Standard and Science School of Materials Science and Engineering Seoul National University Seoul Korea

ISBN: (纸本)0780378725

For the first time, we have investigated the effect of ozone (O/sub 3/) pre-treatment on the bias temperature instability (BTI) characteristics of high-k gate dielectrics. We found that O/sub 3/ pre-treatment improved NBTI and the electrical characteristics of HfAlON gate dielectric. We suggest that O/sub 3/ pre-treatment effectively suppresses the incorporation of the impurities (such as nitrogen (N), hydrogen (H) and water related species), resulting in the improvement of NBTI characteristics (-2.32 V operating voltage for 10 years lifetime). For the PBTI characteristics, the high-k gate dielectric with poly-Si gate electrode was severely degraded. We suggest that dopants (such as arsenic (As) and phosphorus (P)) in the gate electrode of nMOSFETs diffuse into the gate dielectrics, causing the severe degradation of PBTI characteristics (/spl sim/1.1 V operating voltage for 10 years lifetime). We believe that the optimization in the high-k gate stack can improve the PBTI characteristics by suppressing the dopants incorporation.

关键词： Niobium compounds Titanium compounds Electric variables dielectrics Voltage Electrodes degradation Temperature Impurities Nitrogen

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Highly scalable and CMOS-compatible STTM cell technology

Highly scalable and CMOS-compatible STTM cell technology

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International Electron devices Meeting (IEdM)

作者： S.J. Ahn G.H. Koh K.W. Kwon S.J. Baik G.T. Jung Y.N. Hwang H.S. Jeong Kinam Kim Advanced Technology Develoument Device Solution Network Samsung Electronics Company Limited Yongin si Gyeonggi South Korea DRAM Desien 3 Device Solution Network Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Process Develooment Semiconductor R&D Center Device Solution Network Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Advanced Technology Development Device Solution Network Samsung Electronics Co.LTD Yongin-City Kyunggi-Do Korea

The technological challenges associated with STTM (scalable two transistor memory) cells were reviewed. First of all, the basic operating principles of the memory cell are discussed. This is followed by the introduction of the memory array formation and co-process of the I/O transistor, applying a 0.24 /spl mu/m design rule test vehicle. A new cell structure of a surrounded gate STTM structure is introduced. In addition, the process technology and the performance of the memory cell are presented.

关键词： CMOS technology Threshold voltage random access memory Transistors Flash memory Boron Writing Electrons research and development Testing

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