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Microsphere-assisted hyperspectral imaging:super-resolution,non-destructive metrology for semiconductor devices

Light(Science & Applications) 2024年第6期13卷 1098-1111页

作者： Jangryul Park Youngsun Choi Soonyang Kwon Youngjun Lee Jiwoong Kim Jae-joon Kim Jihye Lee Jeongho Ahn Hidong Kwak Yusin Yang Taeyong Jo Myungjun Lee Kwangrak Kim Metrology and Inspection Equipment R&D Team Mechatronics ResearchSamsung Electronics Co.Ltd.1-1 Samsungjeonja-rohwaseong-siGyeonggi-do18848Republic of Korea Process Development Department DRAM Process Development TeamSemiconductor R&D CenterSamsung Electronics Co.Ltd.1-1 Samsungjeonja-rohwaseong-siGyeonggi-do18848Republic of Korea Process Development Department Semiconductor R&D CenterSamsung Electronics Co.Ltd.1-1 Samsungjeonja-rohwaseong-siGyeonggi-do18848Republic of Korea

As semiconductor devices shrink and their manufacturing processes advance,accurately measuring in-cell critical dimensions(Cd)becomes increasingly *** test element group(TEG)measurements are becoming inadequate for representing the fine,repetitive patterns in cell *** non-destructive metrology technologies like optical critical dimension(OCd)are limited due to their large spot diameter of approximately 25μm,which impedes their efficacy for detailed in-cell structural ***,there is a pressing need for small-spot and non-destructive metrology *** address this limitation,we demonstrate a microsphere-assisted hyperspectral imaging(MAHSI)system,specifically designed for small spot optical metrology with *** microsphere-assisted super-resolution imaging,this system achieves an optical resolution of 66 nm within a field of view of 5.6μm×5.6μ*** approach effectively breaks the diffraction limit,significantly enhancing the magnification of the *** MAHSI system incorporating hyperspectral imaging with a wavelength range of 400–790 nm,enables the capture of the reflection spectrum at each camera *** achieved pixel resolution,which is equivalent to the measuring spot size,is 14.4 nm/pixel and the magnification is *** MAHSI system enables measurement of local uniformity in critical areas like corners and edges of drAM cell blocks,areas previously challenging to inspect with conventional OCd *** our knowledge,this approach represents the first global implementation of microsphere-assisted hyperspectral imaging to address the metrology challenges in complex 3d structures of semiconductor devices.

关键词： metrology resolution enable

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Ongoing Evolution of drAM Scaling via Third dimension -Vertically Stacked drAM

Ongoing Evolution of DRAM Scaling via Third Dimension -Verti...

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2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023

作者： Han, J.W. Park, S.H. Jeong, M.Y. Lee, K.S. Kim, K.N. Kim, H.J. Shin, J.C. Park, S.M. Shin, S.H. Park, S.W. Lee, K.S. Lee, J.H. Kim, S.H. Kim, B.C. Jung, M.H. Yoon, I.Y. Kim, H. Jang, S.U. Park, K.J. Kim, Y.K. Kim, I.G. Oh, J.H. Han, S.Y. Kim, B.S. Kuh, B.J. Park, J.M. Dram Technology Development Hwaseong Korea Republic of Next Generation Process Development Samsung R&d Center Hwaseong Korea Republic of

ISBN: (纸本)9784863488069

For the past decades, the density of drAM has been remarkably increased by making access transistors and capacitors smaller in size per unit area. However, shrinking devices far beyond the 10 nm process node increasingly poses process and reliability challenges. As Flash technology made a pivotal and successful innovation via 3d NANd, drAM technology may also adopt vertical stacking memory cells. Vertically stacked drAM (VS-drAM) continues to increase bit density on a die by increasing the number of layers along with reducing the size of the transistor. In this paper, the opportunities and challenges of VS-drAM are discussed. © 2023 JSAP.

关键词： dynamic random access storage

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domain Adaptation based Fin Height Measurement for drAM 5

Domain Adaptation based Fin Height Measurement for DRAM

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5th IEEE International Women in Technology Conference, WINTECHCON 2024

作者： Singh, ramya Bagavath Sultania, Gaurav Pedapudi, Lakshmi Narayana Ahn, Joonyoung Song, Je Ung Ahn, Hyomin Smart Equipment Solutions Group Samsung Semiconductor India Research Bangalore India Advanced Process Development Team 4 Semiconductor R&D Center Hwaseong Korea Republic of

ISBN: (纸本)9798350374070

Fin Height is critical quality parameter of drAM device and its measurement is destructive process. This measurement process has some disadvantages – destroying wafer/chips, limitation on number of chips for measurement leads to less data samples, and its availability towards end of production cycle. Ability of system to predict fin height early/mid production cycle serves vital role to reduce redundancy and save losses in the production pipeline. With the advent of Spectroscopic methods like Ellipsometry (SE), reflectometry, Interferometry, it is possible to capture spectral characteristics of devices in non-destructive framework. ML/dL modelling of spectrum data learns fin height characteristics and aids prediction. Simulation of drAM for spectrum data enables more learning data, helps to enhance fin height prediction by not just data augmentation technique of simulated data to real data. We adopt and employ domain Adaptation (dA) methods for regression problem where dA mostly dealt with classification problem. We demonstrate significant improvement in fin height prediction accuracy by using simulated data in addition to real data via various domain Adaptation methods. © 2024 IEEE.

关键词： dynamic random access storage

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Improved Clearance of Host Cell Protein Impurities at the Polishing Purification Step Using Multimodal Chromatography

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SSrN 2024年

作者： Hutchinson, Jack Lu, Yali Grew, Lara Cui, Tingting Purification Process Sciences BioPharmaceuticals Development BioPharmaceuticals R&D AstraZeneca Cambridge United Kingdom Analytical Sciences BioPharmaceuticals Development BioPharmaceuticals R&D AstraZeneca Cambridge United Kingdom Analytical Sciences BioPharmaceuticals Development BioPharmaceuticals R&D AstraZeneca Gaithersburg United States Robotics and Automation BioPharmaceuticals Development BioPharmaceuticals R&D AstraZeneca Cambridge United Kingdom

In biotherapeutic protein production, host cell proteins (HCPs) are one of the main process related impurities which must be cleared and controlled through downstream processing. In this paper, we studied a novel therapeutic protein molecule which had a high level of HCP co-purification throughout the downstream process. Here, we focused on the polishing purification step and developed an effective strategy for improving HCP clearance using multimodal chromatography (MMC) resin, Nuvia cPrime. A high throughput process development (HTPd) workflow was used to identify the resin and process conditions which could enable significant HCP clearance while maintaining acceptable product quality and process performance. HCP analysis of gradient elution fractions on multimodal chromatography found that HCPs eluted at the beginning of the gradient, at a lower salt concentration than the therapeutic protein. Based on these findings, a step elution process involving an intermediate low salt wash was developed to clear weak-binding HCPs, while retaining the therapeutic protein on the column. This strategy was highly effective and enabled 80% reduction in total HCP content, including some problematic and difficult to remove candidates such as Peroxiredoxin-1, Serine protease HTrA1, Clusterin and Lipoprotein lipase. © 2024, The Authors. All rights reserved.

关键词： Purification

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Ongoing Evolution of drAM Scaling via Third dimension -Vertically Stacked drAM -

Ongoing Evolution of DRAM Scaling via Third Dimension -Verti...

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Symposium on VLSI Technology

作者： J.W. Han S.H. Park M.Y. Jeong K.S. Lee K.N. Kim H.J. Kim J.C. Shin S.M. Park S.H. Shin S.W. Park J.H. Lee S.H. Kim B.C Kim M.H. Jung I.Y. Yoon H. Kim S.U. Jang K.J. Park Y.K. Kim I.G. Kim J.H Oh S.Y. Han B.S. Kim B.J. Kuh J.M. Park DRAM Technology Development Hwaseong Korea Next Generation Process Development Samsung R&D Center Hwaseong Korea

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reverse Laser Assisted Bonding (r-LAB) Technology for Chiplet Module Bonding on Substrate 24

Reverse Laser Assisted Bonding (R-LAB) Technology for Chiple...

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24th Electronics Packaging Technology Conference, EPTC 2022

作者： Na, SeokHo Gim, MinHo Kim, GaHyeon ryu, dongSu Park, dongJoo Kim, JinYoung Amkor Technology Korea Inc. Advanced Process & Material Development Global R&d Center 150 Songdomirate-ro Yeonsu-gu Incheon Korea Republic of

ISBN: (纸本)9798350398854

There are several chip-to-substrate interconnection technologies in the packaging tool kit such as mass reflow (Mr), thermocompression bonding (TCB) and laser assisted bonding (LAB). Mr is a mature process but has known limitations on fine pitch devices and large/thin substrate packages. TCB has the advantage to minimize bump stress for low-K dielectric devices but its productivity is very low. However, LAB can provide a solution for advanced devices with its localized heating and short bonding time. recently, demand for fine-pitch, Flip Chip bumps and large/thin substrate packages has increased, resulting in industry interest in LAB due to its good quality and high productivity. Amkor Technology invented LAB technology in 2014 and passed qualification for multiple devices from customers through many years of development and has been in high volume production for major customers since 2018. However, as the industry continues to require high bonding performance with various new devices, existing LAB technology may not support all these applications. These devices have led to the development of a new bonding concept, which is reverse laser assisted bonding (r-LAB) technology. r-LAB emits the laser to the bottom side of the substrate through a vacuum stage block, which is opposite laser emission direction to existing LAB. It was developed in 2021 by Amkor Technology and showed promising results for the packages where top LAB does not work. There are several devices that require r-LAB. One is back side metallization (BSM) die. BSM dies are necessary for metal thermal interface material (TIM) applications for high thermal performance packages. Promising results for BSM die were published in recent 72nd ECTC [1]. Other devices that require r-LAB include chiplet module bonding on substrate and drAM packaging in an epoxy molding compound (EMC). A chiplet module is necessary for high-performance applications such as servers, networking, artificial intelligence (AI), graphics

关键词： Substrates

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Barrier-Less W Metallization processes for Low-resistance Contacts at Sub-3 nm Logic devices

Barrier-Less W Metallization Processes for Low-Resistance Co...

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IEEE International Conference on Interconnect Technology

作者： Seongdong Lim Seongheum Choi Jeongik Kim Byungchul Kang daeun Kim Yeji Song donghyun Kim Sanghoon Uhm Chunghwan Shin Taehong Ha rak-Hwan Kim Foundry Process Development Team Semiconductor R&D Center Samsung Electronics Co. Ltd. Hwaseong Republic of Korea

ISBN: (数字)9798350385175

ISBN: (纸本)9798350385182

The low-resistance of middle of line (MOL) contacts has been highlighted as critical for high-performance logic devices. Tungsten (W) has been widely used in MOL, but the relevantly required barrier materials (e.g. TiN) prevented achieving low resistance contacts as the dimension shrinks down. The replacement of high resistance barrier by an enhanced PVd W technology with an excellent step coverage allowed barrier-less W process, but a limited gap-fill performance of PVd W alone is still challenging for ultra-high aspect ratio contacts at sub-3 nm logic devices. In this study, a novel fabrication route of low-resistance barrier-less W contacts has been freshly demonstrated by reinforcing the combination of PVd W and CVd W with an adoption of nucleation process. The result of ASTAr TEM analysis exhibits a single crystallographic orientation in each contact, which is desirable for the low resistivity and reliability. Furthermore, the nucleation-assisted barrier-less W shows dramatically reduced contact resistance compared to the conventional W metallization with barrier, which resulted in significant gain of AC performance in logic devices. The suggested barrier-less W metallization process is strongly believed to be more efficiently applicable to high-performance sub-3 nm logic devices.

关键词： resistance Performance evaluation Fabrication Metallization Tungsten Tin Contact resistance reliability Logic devices Plugs

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defect detection in Photolithographic Patterns Using deep Learning Models Trained on Synthetic data

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SSrN 2024年

作者： Shinde, Prashant P. Pai, Priyadarshini P. Adiga, Shashishekar P. Mayya, K. Subramanya Seo, Yongbeom Hwang, Myungsoo Go, Heeyoung Park, Changmin Samsung Semiconductor India Research Bangalore560048 India Foundry Process Development Team Semiconductor R&D Center Samsung Electronics Seoul Korea Republic of

In the photolithographic process vital to semiconductor manufacturing, various types of defects appear during EUV pattering. due to ever-shrinking pattern size, these defects are extremely small and cause false or missed detection during inspection. Specifically, the lack of defect-annotated quality data with good representation of smaller defects has prohibited deployment of deep learning based defect detection models in fabrication lines. To resolve the problem of data unavailability, we artificially generate scanning electron microscopy (SEM) images of line patterns with known distribution of defects and autonomously annotate them. We then employ state-of-the-art object detection models to investigate defect detection accuracy as a function of defect size, much smaller than the pitch width. We find that the real-time object detector YOLOv8 has the best detection accuracy of 94.2% as compared to EfficientNet, 73.8%, and SSd, 70.4%, with the ability to detect smaller defects. We report the smallest defect size that can be detected reliably. When tested on real SEM data, the YOLOv8 model detected Bridge and Break defects with 84.6% and 78.3% accuracy, respectively. These promising results suggest that synthetic data can be used as an alternative to real-world data in order to develop robust machine-learning models. © 2024, The Authors. All rights reserved.

关键词： Photolithography

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Fourier ptychographic topography

Fourier ptychographic topography

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作者： Wang, Hao Zhu, Jiabei Sung, Jangwoon Hu, Guorong Greene, Joseph Li, Yunzhe Park, Seungbeom Kim, Wookrae Lee, Myungjun Yang, Yusin Tian, Lei Department of Electrical and Computer Engineering Boston University MA02215 United States MI Equipment R&D Team Mechatronics Research Samsung Electronics Co. Ltd. Hwasung18848 Korea Republic of Process Development Semiconductor R&D Center Samsung Electronics Co. Ltd. Hwasung18848 Korea Republic of Department of Biomedical Engineering Boston University MA02215 United States

Topography measurement is essential for surface characterization, semiconductor metrology, and inspection applications. To date, performing high-throughput and accurate topography remains challenging due to the trade-off between field-of-view (FOV) and spatial resolution. Here we demonstrate a novel topography technique based on the reflection-mode Fourier ptychographic microscopy, termed Fourier ptychograhpic topography (FPT).We showthat FPT provides both a wide FOV and high resolution, and achieves nanoscale height reconstruction accuracy. Our FPT prototype is based on a custom-built computational microscope consisting of programmable brightfield and darkfield LEd arrays. The topography reconstruction is performed by a sequential Gauss-Newton-based Fourier ptychographic phase retrieval algorithm augmented with total variation regularization. We achieve a synthetic numerical aperture (NA) of 0.84 and a diffraction-limited resolution of 750 nm, increasing the native objective NA (0.28) by 3×, across a 1.2 × 1.2 mm2 FOV. We experimentally demonstrate the FPT on a variety of reflective samples with different patterned structures. The reconstructed resolution is validated on both amplitude and phase resolution test features. The accuracy of the reconstructed surface profile is benchmarked against high-resolution optical profilometry measurements. In addition, we show that the FPT provides robust surface profile reconstructions even on complex patterns with fine features that cannot be reliably measured by the standard optical profilometer. The spatial and temporal noise of our FPT system is characterized to be 0.529 nm and 0.027 nm, respectively. © 2023 Optica Publishing Group.

关键词： Topography

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Wide-field, high-resolution reflection-mode Fourier ptychographic microscopy

Wide-field, high-resolution reflection-mode Fourier ptychogr...

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2023 digital Holography and Three-dimensional Imaging, dH 2023 in Optica Imaging Congress - Part of Imaging and Applied Optics Congress 2023

We demonstrate a novel topography technique based on the reflection-mode Fourier ptychographic microscopy, termed Fourier ptychograhpic topography (FPT), to provide a wide field-of-view, high resolution, and nanoscale... 详细信息

ISBN: (纸本)9781957171289

关键词： Topography

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