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International Electron devices Meeting (IEdM)

作者： I.G. Baek d.C. Kim M.J. Lee H.-J. Kim E.K. Yim M.S. Lee J.E. Lee S.E. Ahn S. Seo J.H. Lee J.C. Park Y.K. Cha S.O. Park H.S. Kim I.K. Yoo U. Chung J.T. Moon B.I. ryu Process Development Team Samsung Electronics Co. Ltd. Yongin si South Korea Process Development Team Semiconductor R&D Center Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Devices Lab. Samsung Advanced Institute of Technology Yongin-City Kyeonggi-Do Korea Process Development Team Samsung Electronics Co. Ltd.

Feasibility of the multi-layer cross-point structured binary oxide resistive memory (OxrrAM) has been tested for next generation non-volatile random access high density data storage application. Novel plug contact type bottom electrode (plug-BE) could reduce active memory cell diameter down to 50nm with smaller operation current and improved switching distributions. With 2 additional masks, one layer of plug-BE included cross-point memory array could be added on top of another one. No signal of inter-layer interference has been observed. Also, prototype binary oxide based diodes have been fabricated for the purpose of suppressing intra-layer interference of cross-point memory array

关键词： Electrodes Testing Memory Plugs Energy consumption CMOS technology Moon research and development Consumer electronics Electronic mail

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S-rCAT (sphere-shaped-recess-channel-array transistor) technology for 70nm drAM feature size and beyond

S-RCAT (sphere-shaped-recess-channel-array transistor) techn...

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Symposium on VLSI Technology

作者： J.V. Kim H.J. Oh d.S. Woo Y.S. Lee d.H. Kim S.E. Kim G.W. Ha H.J. Kim N.J. Kang J.M. Park Y.S. Hwang d.I. Kim B.J. Park M. Huh B.H. Lee S.B. Kim M.H. Cho M.Y. Jung Y.I. Kim C. Jin d.W. Shin M.S. Shim C.S. Lee W.S. Lee J.C. Park G.Y. Jin Y.J. Park Kinam Kim Samsung Electronics Co. Yongin-City Kyunggi-Do KOREA Advanced Technology Development Semiconductor Research and Development Division CAE Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Advanced Technology Development Semiconductor R&D Division CAE Advanced Technology Development Semiconductor Research and Development Division Process Technology Team Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Process Technology Team

For the first time, S-rCAT (sphere-shaped-recess-channel-array transistor) technology has been successfully developed in a 2Gb density drAM with 70nm feature size. It is a modified structure of the rCAT (recess-channel-array transistor) and shows an excellent scalability of recessed-channel structure to sub-50nm feature size. The S-rCAT demonstrated superior characteristics in dIBL, subthreshold swing (SW), body effect, junction leakage current and data retention time, comparing to the rCAT structure, in this paper, S-rCAT is proved to be the most promising drAM array transistor suitable for sub-50nm and mobile applications.

关键词： random access memory Paper technology Transistors Neck research and development Computer aided engineering Very large scale integration

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The Vth controllability of 5nm body-tied CMOS FinFET

The Vth controllability of 5nm body-tied CMOS FinFET

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International Symposium on VLSI Technology, Systems and Applications

作者： Hye Jin Cho Jeong dong Choe Jeongnam Han dongchan Kim Heungsik Park doohoon Goo Ming Li Chang Woo Oh dong-Won Kim Tae Yong Kim Choong-Ho Lee donggun Park Kinam Kim Byung-Il ryu Semiconductor Research & Development Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Device Research Team Process Development Team Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Semicond. R&D Div. Samsung Electron. Co. Gyeonggi-Do South Korea

ISBN: (纸本)078039058X

In this paper, we demonstrate a 5nm width body-tied CMOS finFET on bulk Si for the first time. Also the threshold voltage control of the 5nm finFET is shown by using channel and pocket doping profile optimization along the narrow active fin. The excellent performance of finFET such as an excellent subthreshold swing (SS), and drain induced barrier lowering (dIBL) characteristics were found. And the systemic analyses of electrical characteristics dependencies on the fin width were evaluated for various fin width (5 /spl sim/ 100nm).

关键词： Controllability FinFETs CMOS process CMOS technology MOS devices Manufacturing processes Immune system doping Threshold voltage Voltage control

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Advanced Al damascene process for Fine Trench Under 70nm design rule

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MrS Online Proceedings Library 2005年第1期863卷 B8.23-1-B8.23-6页

作者： Sung Ho Han Kyung-In Choi Sera Yun Jeong Heon Park Won Sok Lee Sang Woo Lee Gil Heyun Choi Change Kee Hong Sung Tae Kim Uin Chung Joo Tae Moon Byung-Il ryu Process Development Team Semiconductor R&D Center Samsung Electronics Co. Ltd. Yongin-City Korea

due to a rapid shrinkage in memory devices, backned of the line process experiences great difficulties, especially Al metallization. Furthermore, there is a continuous demands in low line resistance in order to promote device performances. In this article, Al damascene process is proposed as compared to Al patterning process, which suffers from inherent pattering issue at a fine pitch under 70nm. The most difficulties in the development of Al damascene process were to form a stable and void free Al in fine trench and to obtain scratch and corrosions free Al surface. In this study, 50nm beyond fill was successfully achieved by “bottom up growth” of CVd Al. For the process, CVd Al by using Methylpyrroridine Alane (MPA) precursor was deposited on a stacked film of CVd TiN and PVd TiN as a wetting layer, which was followed by PVd Al and reflow, then the Al surface was polished with colloidal silica based slurry. In addition, electrical property of Al scheme and W scheme was compared with damascene pattern, along with which we demonstrated that around 36% decrease in parasitic capacitance is achievable by decrease of metal line height from 3500A to 1000A on simulation test implying that device performance could be enhanced.

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Fabrication of 3d trench PZT capacitors for 256Mbit FrAM device application

Fabrication of 3D trench PZT capacitors for 256Mbit FRAM dev...

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International Electron devices Meeting (IEdM)

作者： June-Mo Koo Bum-Seok Seo Sukpil Kim Sangmin Shin Jung-Hyun Lee Hionsuck Baik Jang-Ho Lee Jun Ho Lee Byoung-Jae Bae Ji-Eun Lim dong-Chul Yoo Soon-Oh Park Hee-Suk Kim Hee Han Sunggi Baik Jae-Young Choi Yong Jun Park Youngsoo Park Nano Devices Laboratory Samsung Advanced Institute of Technology Yongin si South Korea Nano Fabrication Center Samsung Advanced Institute of Technology Yongin si South Korea AE Center Samsung Advanced Institute of Technology Yongin si South Korea Process Development Team Semiconductor R&D Division Samsung Electronics Company Limited Yongin si South Korea Department of Materials Science and Engineering Pohang University of Science and Technology Pohang South Korea Pohang Accelerator Laboratory Pohang University of Science and Technology Pohang South Korea

ISBN: (纸本)078039268x

We fabricated trench PbZr x Ti 1-x O 3 (PZT) capacitors that can be used in 256Mbit 1T-1C FrAM devices. The capacitor has 0.25mum diameter and 0.4mum depth. Three layers, Ir(20nm)/PZT(60nm)/Ir(20nm), were deposited in SiO 2 trench holes by ALd and MOCVd. Both columnar and granular grains were formed on the sidewalls of the trench capacitors, and their relative portion had strong size dependence. The trench capacitors with more columnar PZT grains showed good switching behavior under 2.1V external bias and 19 to 24 muC/cm 2 remnant polarization

关键词： Fabrication Capacitors random access memory Ferroelectric films Nonvolatile memory Polarization Materials science and technology Laboratories MOCVd Ferroelectric materials

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The automated backup solution - Safeguarding the communications network infrastructure

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BELL LABS TECHNICAL JOUrNAL 2004年第2期9卷 59-84页

作者： Lennert, JF retzner, W rodgers, MG ruel, BG Sundararajan, S Wolfson, Pd Member of technical staff R&D Operations and Administration Module (AM) Complex Department Lucent Technologies Inc. Member of technical staff Lucent Technologies Technical Support Services (TSS) Department Lucent Technologies Inc. Technical manager Software Change Administration and Notification System (SCANS) R&D Operations and Administration Module (AM) Complex Department Lucent Technologies Inc. Technical manager Ongoing Support (OGS) R&D Operations and Administration Module (AM) Complex Department Lucent Technologies Inc. Technical manager Robust Process Automation (RPA) R&D Operations and Administration Module (AM) Complex Department Lucent Technologies Inc. Member of technical staff R&D Operations and Administration Module (AM) Complex Department Lucent Technologies Inc. Director Convergence Solutions R&D organization R&D operations and AM complex software development Lucent Technologies Inc

The communications network infrastructure of a country plays a critical role in preserving national security, economic stability, and public safety in a local, national, or international crisis. This paper describes how a telecommunications switch and attached adjunct computer server at a telephone network switching center can be used to provide a reliable, automated, cost-effective way to perform the backup and remote storage of communications infrastructure software and data. The implementation of this backup and storage process-called the Automated Backup Solution-would make infrastructure software and data readily available in a crisis (e.g., a network outage or terrorist attack) and would speed up the restoration of the communications infrastructure in the event of a disaster The Automated Backup Solution, which uses a high-bandwidth, transmission control protocol/Internet protocol (TCP/IP)-capable adjunct server, is an economical alternative to the physical media and the costly, unreliable, manual backup process that are currently used for backup and storage. This paper also demonstrates the usefulness of the Automated Backup Solution in preserving homeland security and offers insights into ways of implementing eleven communications-industry best practices. (C) 2004 Lucent Technologies Inc.

关键词： COMMUNICATION INFrASTrUCTUrE (Economics) TELECOMMUNICATION systems TErrOrISM TELECOMMUNICATION

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A Highly Manufacturadle Low-k ALd-SiBN process for 60nm NANd Flash devices and Beyond

A Highly Manufacturadle Low-k ALD-SiBN Process for 60nm NAND...

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IEEE International Electron devices Meeting, 2004 IEdM

作者： Kim, Jin-Gyun Ahn, Jae-Young Kim, Hong-Suk Lim, Ju-Wan Kim, Chae-Ho Shu, Hoka Hasebe, Kazuhide Hur, Sung-Hoi Park, Jong-Ho Kim, Hee-Seok Shin, Yu-Gyun Chung, U-In Moon, Joo-Tae Process Development Team Technology Development Team Semiconductor R&D Center Samsung Electronics Co. LTD Gyeonggi-Do Yongin-City449-711 Korea Republic of Process Engineering Section Thermal Processing Systems BU Tokyo Electron Ltd. 650 Mitsuzawa Hosaka-cho Yamanashi Nirasaki407-0192 Japan

For the first time, low-k dielectric ALd-SiBN (Atomic Layer deposition) is successfully developed and applied on poly-Si/WSix gate as a spacer for reduction of parasitic capacitance between the cells. ALd-SiBN deposition is performed at 630°C using dichlorosilane (SiH2Cl2-dCS), boron-trichloride (BCl3) and ammonia (NH3) as precursors. Compared with the conventional silicon nitride, ALd-SiBN exhibits similar film properties at lower dielectric constant. ALd-SiBN layer is deposited on poly-Si/WSix stack gate in 90nm NANd flash device. A significant reduction (>15%) of the floating-gate coupling voltage is achieved by employing SiBN compared with SiN spacer. In addition, excellent data retention characteristics (@HTS) is identified by applying lowk dielectric SiBN layer as a spacer on 90nm NANd flash device. © 2004 IEEE.

关键词： Chlorine compounds

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A mechanically enhanced storage node for virtually unlimited height (MESH) capacitor aiming at sub 70nm drAMs

A mechanically enhanced storage node for virtually unlimited...

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International Electron devices Meeting (IEdM)

作者： d.H. Kim J.Y. Kim M. Huh Y.S. Hwang J.M. Park d.H. Han d.I. Kim M.H. Cho B.H. Lee H.K. Hwang J.W. Song N.J. Kang G.W. Ha S.S. Song M.S. Shim S.E. Kim J.M. Kwon B.J. Park H.J. Oh H.J. Kim d.S. Woo M.Y. Jeong Y.I. Kim Y.S. Lee J.C. Shin J.W. Seo S.S. Jeong K.H. Yoon T.H. Ahn J.B. Lee Y.W. Hyung S.J. Park H.S. Kim W.T. Choi G.Y. Jin Y.G. Park Kinam Kim Advanced Technology Development Team Process Technology Team Semiconductor R&D Div Samsung Electronics Co Kiheung-Eup Yongin-City Kyunggi-Do Korea

Fully reliable lean-free stacked capacitor, with the meshes of the supporter made of Si/sub 3/N/sub 4/, has been successfully developed on 80nm COB drAM application. This novel process terminates persistent problems caused by mechanical instability of storage node with high aspect ratio. With Mechanically Enhanced Storage node for virtually unlimited Height (MESH), the cell capacitance over 30fF/cell has been obtained by using conventional MIS dielectric with an equivalent 2.3nm oxide thickness. This inherently lean-free capacitor makes it possible extending the existing MIS dielectric technology to sub-70nm OCS (one cylindrical storage node) drAMs.

关键词： Capacitors random access memory Tin Capacitance dielectric materials Bridge circuits Glass Strips Manufacturing processes Semiconductor device manufacture

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STTM - Promising nanoelectronic drAM device

STTM - Promising nanoelectronic DRAM device

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2004 4th IEEE Conference on Nanotechnology

作者： Seung Jae Baik Zongliang Huo Seung-Hyun Lim Process Development Team Semiconductor R&D Center Samsung Electronics Co. LTD. San#24 Nongseo-Ri Giheung-Eup Yongin-City Gyeonggi-Do Korea 449-711

ISBN: (纸本)0780385365

We have examined STTM as the alternative to drAM in terms of scalability, operation power, and sensing signal. The characteristics of STTM are shown to strongly depend on those of vertical transistor. To obtain maximum performance, fully depleted vertical transistor is essential. Moreover, it is shown that scaling below 50nm could exhibit long enough retention time for nonvolatile random access memory application.

关键词： drAM chips nanoelectronics nanoelectronic drAM device operation power sensing signal vertical transistor retention time nonvolatile random access memory application scalable two transistor memory scalability

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EFFECTS OF MOdIFICATION OF THE CArBIdE CHArACTErISTICS THrOUGH GrAIN BOUNdArY SErrATION ON CrEEP-FATIGUE LIFE IN AUSTENITIC STAINLESS STEELS

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Acta Metallurgica Sinica(English Letters) 2004年第5期17卷 632-638页

作者： K.J.Kim H.U.Hong K.S.Min S.W.Nam Dept. of Materials Science and Engineering Korea Advanced Institute of Science and Technology 373-1 Guseong-dong Yuseong-gu Deajeon 305-701 KoreaPosco Technical Research Laboratory #1 Koedong-dong Nam-gu Pohang 790-300 KoreaProcess Solution Development Team 1 LCD R&D Center AMLCD Division Device Solution Network Samsung Electronics Co. LTD.San 24 Nongseo-ri Giheung-eup Yongin Gyeonggi-do 449-771 KoreaDept. of Materials Science and Engineering Korea Advanced Institute of Science and Technology 373-1 Guseong-dong Yuseong-gu Deajeon 305-701 Korea

Modification of the carbide characteristics through the grain boundary serration is investigated, using an AISI 316 and 304 stainless steels. In both steels, triangular carbides were observed at straight grain boundaries while planar carbides were observed at the serrated grain boundaries. The serrated grain boundary energy is observed to be much lower than that of the straight one. Therefore, the carbide morphology is found to be changed from triangular to planar along the serrated boundary to reduce the interfacial energy between the carbide and the matrix. The creep-fatigue properties of these steels at 873K have been investigated. The creep-fatigue life of the sample with planar carbide at the serrated grain boundary was found to be much longer than that with triangular carbide at the straight one. These results imply that the planar carbides with lower interfacial energy have higher cavitation resistance, resulting in the retardation of cavity nucleation and growth to increase creep-fatigue life.

关键词： cavity nucleation factor grain boundary serration carbide morphology austenitic stainless steel grain boundary cavitation

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