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Preclinical characterization of a new liquid “immune globulin intravenous (human), 10% triple virally reduced solution” (IGIV, 10%TVr)

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Journal of Allergy and Clinical Immunology 2004年第2期113卷 S45-S45页

作者： W. Teschner W. Auer L. Pichler U. Bölzlbauer A. Butterweck H. Schwarz Product and Process Development Immunoglobulin/Albumin Baxter BioScience Vienna Austria Toxicology Baxter BioScience Vienna Austria Pharmacology Toxicology and Preclinicals Baxter BioScience Vienna Austria Product and Process Development Immunology/Albumin Baxter BioScience Vienna Austria Global Preclinical R&D BioPharmaceuticals Baxter BioScience Vienna Austria

rationale In preclinical testing the efficacy, safety, pharmacokinetics, and toxicity of a new liquid 10% intravenous immunoglobulin preparation (IGIV, 10%TVr) was compared with Gammagard® S/d, a licensed lyophilized immunoglobulin for intravenous infusion. Methods Efficacy is proved in vivo by mouse protection testing and in vitro by opsonization and affinity chromatography using protein A Sepharose. The blood-pressure-lowering effect in spontaneously hypertensive rats and the bronchospastic effect in guinea pigs are used as indicators of the anaphylactoid potential. Pharmacokinetics in rats is evaluated by the variables “in vivo recovery” and “half-life” after a single intravenous dose of 1000 mg/kg. Thrombogenicity is assessed in a rabbit model and the influence of the products on vital functions like cardiovascular, respiratory and blood coagulation variables is tested in dogs. Acute toxicity studies are carried out in mice and rats. results The mouse protection test showed that the protective activity against systemic bacterial infections of IGIV, 10%TVr is at least as good as the reference Gammagard S/d. This result is supported by the broad spectrum of antibodies in high titers against bacteria and viruses and the high functional integrity of the IgG molecule (≥90% functional intact IgG) in IGIV, 10%TVr. In safety and thrombogenicity studies, no adverse effects of IGIV, 10%TVr were observed. Pharmacokinetic studies showed no statistically significant differences between the two products. In the acute toxicity animal studies, IGIV, 10%TVr was better tolerated than the reference Gammagard S/d. Conclusions Liquid IGIV, 10%TVr combines excellent qualities of efficacy, safety and tolerability.

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New approaches to improve the endurance of TiN/HfO/sub 2//TiN capacitor during the back-end process for 70nm drAM device

New approaches to improve the endurance of TiN/HfO/sub 2//Ti...

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International Electron devices Meeting (IEdM)

作者： Jae Hyoung Choi Jeong-Hee Chung Se-Hoon Oh Jeong Sik Choi Cha-Young Yoo Sung-Tae Kim U-In Chung Joo-Tae Moon Process Development Team Semiconductor R&D Division Yongin-City Gyeonggi-Do KOREA

ISBN: (纸本)0780378725

We have successfully developed a MIM capacitor process technology with a HfO/sub 2/ single layer deposited by ALd (atomic layer deposition), where a Hf(NEtMe)4 and CVd-TiN cylinder-type storage-node were used as a Hf liquid source and bottom electrode for 90 nm-scale drAMs. Our experimental results indicated that NH/sub 3/-plasma treatment on HfO/sub 2/ film promoted crystallization below 400/spl deg/C as well as the formation of a HfO/sub x/N/sub y/ layer on the surface of the HfO/sub 2/ film. With this treatment, it was possible to solve the degradation problem of the leakage current depending on deposition method of the top electrode, and a stable leakage current without degradation was obtained up to 550/spl deg/C. As a result, a TiN/HfO/sub 2//TiN (TIT) capacitor with 1.4 /spl mu/m-height storage node was successfully demonstrated with stable leakage current of 1fA/cell at +1.2 V and high cell capacitance of 40 fF after metal-2 integration.

关键词： Tin Hafnium oxide Leakage current Electrodes degradation MIM capacitors Atomic layer deposition Crystallization Surface treatment Capacitance

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Quantitative evaluation of grid size effect on Cd uniformity improvement

Quantitative evaluation of grid size effect on CD uniformity...

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International Conference on Microprocesses and Nanotechnology

作者： doo-Youl Lee Sung-Woo Lee Gi-Sung Yeo Jung-Hyeon Lee Han-Ku Cho Woo-Sung Han Semiconductor R&D center Samsung Electronics Process Development Team Yongin si Gyeonggi South Korea

In this paper, evaluation of grid size effect on Cd uniformity was investigated. The reduction of the grid size can more elaborately correct Cd variation by reducing the local mask uniformity and is expected to decrea... 详细信息

ISBN: (纸本)4891140402

关键词： Size measurement Size control Mesh generation research and development Electronic mail Error correction Printing random access memory data handling

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TiN/HfO/sub 2//TiN capacitor technology applicable to 70 nm generation drAMs

TiN/HfO/sub 2//TiN capacitor technology applicable to 70 nm ...

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Symposium on VLSI Technology

作者： Se-Hoon Oh Jeong-Hee Chung Jae-Hyoung Choi Cha-Young Yoo Young Sun Kim Sung Tae Kim U-In Chung Joo Tae Moon Process Development Team Semiconductor R&D Division Samsung Electronics Company Limited Yongin si Kyunggi South Korea

ISBN: (纸本)489114033X

We have developed a cylindrical TiN/HfO/sub 2//TiN (TIT) capacitor for 70 nm drAMs application. TIT capacitors with HfO/sub 2/ films deposited by ALd(Atomic Layer deposition) using Hf(NEtMe)/sub 4/ precursor and O/sub 2/ plasma as a reactant is shown to be applicable to drAM device below 70 nm design rule for the first time. It shows the thermal budget endurance against back-end process of drAM device as well as the very low enough Toxeq of about 13 /spl Aring/ to provide the sufficient cell capacitance.

关键词： Tin Hafnium oxide random access memory Leakage current Plasma temperature dielectric thin films MIM capacitors Capacitance Thermal degradation High-K gate dielectrics

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The P-SOG filling Shallow Trench Isolation technology for sub-70 nm device

The P-SOG filling Shallow Trench Isolation technology for su...

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Symposium on VLSI Technology

作者： Jin-Hwa Heo Soo-Jin Hong Guk-Hyon Yon Yu-Gyun Shin K. Fujihara U-In Chung Joo-Tae Moon Process Development Eam Semiconductor R&D Center Samsung Electronics Company Limited Yongin si Kyunggi South Korea

ISBN: (纸本)489114033X

A novel Polysilazane-based inorganic Spin-On-Glass filling Shallow Trench Isolation (P-SOG filling STI) technology is developed for sub-70 nm devices, for the first time. A key processing step of this P-SOG filling STI technology is annealing after a CMP process. The post-CMP P-SOG annealing eliminates a field oxide recess problem. This technology shows good electrical characteristics compared with a HdP oxide filling STI. The P-SOG filling STI is a promising candidate for the future isolation technology.

关键词： Filling Isolation technology Annealing random access memory Electric variables Wet etching Current measurement Leakage current Moon research and development

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Most efficient alternative as a way of sub-80 nm contact holes and trenches formation

Most efficient alternative as a way of sub-80 nm contact hol...

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International Conference on Microprocesses and Nanotechnology

作者： Jung Hwan Hah Jin-Young Yoon Hata Mitsuhiro Hyun-Woo Kim Sang-Gyun Woo Han-Ku Cho Woo-Sung Han Process Development Team Semiconductor R&D Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea

ISBN: (纸本)4891140402

In this paper, we compared three processes to confirm their feasibility and extract the weak and strong aspects of each process. Each process was evaluated with a mask having 1:1 square array and the isolated contact hole patterns of various contact Cd and pitches and then its appropriate or best layout was determined or recommended for real device application.

关键词： Lithography Chemical technology research and development Electronics industry Page description languages Chemical processes

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Writing current reduction for high-density phase-change rAM

Writing current reduction for high-density phase-change RAM

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International Electron devices Meeting (IEdM)

作者： Y.N. Hwang S.H. Lee S.J. Ahn S.Y. Lee K.C. ryoo H.S. Hong H.C. Koo F. Yeung J.H. Oh H.J. Kim W.C. Jeong J.H. Park H. Horii Y.H. Ha J.H. Yi G.H. Koh G.T. Jeong H.S. Jeong Kinam Kim Advanced Technology Development Semiconductor R&D Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Process Development Semiconductor R&D Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea

By developing a chalcogenide memory element that can be operated at low writing current, we have demonstrated the possibility of high-density phase-change random access memory. We have investigated the phase transition behaviors as a function of various process factors including contact size, cell size and thickness, doping concentration in chalcogenide material and cell structure. As a result, we have observed that the writing current is reduced down to 0.7 mA.

关键词： Writing Phase change random access memory Power system dynamics doping Fabrication Size control process control Thickness control Electrodes Electrical resistance measurement

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Approach to critical dimension error budget analysis and specification estimation by the Monte Carlo method

Journal of Vacuum Science & Technology B: Microelectronics a...

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Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures processing, Measurement, and Phenomena 2003年第6期21卷 3120-3123页

作者： Sung-Woo Lee Gi-Sung Yeo Jung-Hyeon Lee Han-Ku Cho Woo-Sung Han Process Development Team Semiconductor R&D Center Samsung Electronics San No. 24 Nongseo-Ri Kiheung-Eup Yongin-City Kyunggi-Do 499-711 Korea

A systematic approach to determine the specifications for process latitude in a 80 nm node device is suggested based on critical dimension (Cd) error budget analysis using the Monte Carlo method. Using an aerial image simulation with the Gaussian convolution model, Cd error budget analysis is performed on line/space (L/S), island, and contact patterns in a 90 nm node device. The portions contributed by mask uniformity are 60%, 66%, and 50% for the L/S, island, and contact patterns, respectively, and they occupy a dominant part in comparison with ones from other factors. The contact pattern occupies 12% for focus variation, which shows the larger portion than the analysis result for L/S and island patterns. The contribution of the 1 nm grid size in the mask layout is approximately 10% of the in-field uniformity. The residual terms which include variations from aberration, inaccurate measurement, postexposure baking, development, line-edge roughness, etc. occupy 21% for L/S and contact patterns, and 16% for island patterns. Based on Cd error budget analysis, specifications in a 80 nm node device are calculated. The portion contributed by each process variation in the 80 nm node device is assumed to be approximately equal to those in the 90 nm node device. The specifications for mask uniformity are 6.8 and 5.8 nm for L/S and island patterns, respectively, while they are 2.9 nm for the contact pattern. The small margin for the contact pattern is due to a large mask error enhancement factor. The contact pattern shows a drastic decrease in flare, focus margin, illumination uniformity, and mask transmittance. In the 80 nm node device, the grid size of the mask layout to generate the patterns should be reduced to less than 0.3 nm.

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Full integration and reliability evaluation of phase-change rAM based on 0.24 /spl mu/m-CMOS technologies

Full integration and reliability evaluation of phase-change ...

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Symposium on VLSI Technology

作者： Y.N. Hwang J.S. Hong S.H. Lee S.J. Ahn G.T. Jeong G.H. Koh J.H. Oh H.J. Kim W.C. Jeong S.Y. Lee J.H. Park K.C. ryoo H. Horii Y.H. Ha J.H. Yi W.Y. Cho Y.T. Kim K.H. Lee S.H. Joo S.O. Park U.I. Chung H.S. Jeong Kinam Kim Semiconductor R&D Div. Samsung Electronics Co. Ltd Yongin Kyunggi-Do Korea Process Development Semiconductor R&D Div. Samsung Electronics Co. Ltd Yongin Kyunggi-Do Korea

We have fully integrated a nonvolatile random access memory by successfully incorporating a reversibly phase-changeable chalcogenide memory element with MOS transistor. As well as basic characteristics of the memory operation, we have also observed reliable performances of the device on hot temperature operation, endurance against repetitive phase transition, writing imprint, reading disturbance and data retention.

关键词： CMOS technology Phase change random access memory Nonvolatile memory random access memory Writing Crystallization Amorphous materials Plasma confinement Phase change memory MOSFETs

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Performance improvement of MOSFET with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate gate dielectric and CVd-TaN metal gate deposited by TAIMATA

Performance improvement of MOSFET with HfO/sub 2/-Al/sub 2/O...

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International Electron devices Meeting (IEdM)

作者： Seong Geon Park You Kyoung Lee Sang Bom Kang Hyung Suk Jung Seok Joo doh Jong-Ho Lee Jae Ho Choi Gyeong Hoon Kim Gil Heyun Choi U In Chung Joo Tae Moon Process Development Team 2 Semiconductor R&D Center Samsung Electronics Company Limited Gyeonggi South Korea Advanced Process Development Team System LSI Business Samsung Electronics Company Limited South Korea Evertek Company Limited Songnam Gyeonggi South Korea

ISBN: (纸本)0780378725

For the first time, we integrated a HfO/sub 2/-Al/sub 2/O/sub 3/ laminate gate dielectric with a CVd-TaN metal gate deposited by TAIMATA (tertiaryamylimidotris dimethylamidotantalum) in n/pMOSFETs. It was found that TaN films with low impurity contents were required for optimized capacitance. Together with a slight improvement of the transconductance and a substantial gain in inversion EOT with HfAlO/TaN, improved current drivability was observed in comparison to nitrided-SiO/sub 2//poly-Si and HfAlON/poly-Si with similar EOTs. In addition, CVd-TaN resulted in improved J/sub g/ characteristics, showing F-N tunneling behavior with an effective barrier height of 1.1 eV in nMOS in the inversion region. These results suggest that a CVd-TaN metal gate is necessary for the implementation and scaling of high-k gate dielectrics.

关键词： MOSFET circuits Hafnium oxide Laminates Capacitance High-K gate dielectrics Leakage current High K dielectric materials Gas insulated transmission lines Moon research and development

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