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International Electron devices Meeting (IEdM)

作者： S.B. Kang H.S. Kim K.J. Moon W.H. Sohn G.H. Choi S.H. Kim N.J. Bae U.I. Chung J.T. Moon Process Development Team Semiconductor R&D Center Samsung Electronics Company Limited Yongin si Gyeonggi South Korea CVD Division COMTECS Limited Daegu South Korea

A novel CVd-cobalt process which enables a uniform salicidation even in novel MOS device structures with complex shape is developed for the first time. With CVd-cobalt salicidation, identical values of low sheet resistance can be realized on actives and gates regardless of the surrounding geometry, due to its excellent conformality. In addition, a low contact resistance can be obtained in small metal/active contacts even with high post thermal budget when CVd-Co is applied as an ohmic layer due to its conformality and inertness with the dopants. CVd-cobalt is a needed and suitable solution for the salicidation and silicidation of not only the continuously scaling conventional CMOS, but also the emerging next generation of devices with complex shapes and structures such as vertical and 3d FET.

关键词： Silicidation MOS devices Shape Conductivity Temperature Chemical analysis Moon Geometry Thermal resistance Semiconductor films

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Fabrication of HfSiON gate dielectrics by plasma oxidation and nitridation, optimized for 65 nm mode low power CMOS applications

Fabrication of HfSiON gate dielectrics by plasma oxidation a...

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Symposium on VLSI Technology

作者： S. Inumiya K. Sekine S. Niwa A. Kaneko M. Sato T. Watanabe H. Fukui Y. Kamata M. Koyama A. Nishiyama M. Takayanagi K. Eguchi Y. Tsunashima Process and Manufacturing Engineering Center Process and Manufacturing Engineering Center Yokohama Japan SoC Research & Development Center Semiconductor Company Yokohama Japan Advanced LSI Technology Laboratory R&D Center Toshiba Corporation Isogo-ku Yokohama Japan SoC Research & Development Center Semiconductor Company

Fabrication process of HfSiON gate dielectrics by plasma oxidation of CVd Hf silicate followed by plasma nitridation was developed. Thanks to the high quality ultrathin interfacial layer formed by internal plasma oxidation, electron mobility of 240 cm/sup 2//Vs@0.8 MV/cm (85% of SiO/sub 2/) and hole mobility of 73 cm/sup 2//Vs@0.5 MV/cm (93% of SiON) were successfully achieved. The developed process will be promising for the production of low power CMOS devices in the near future.

关键词： Fabrication dielectrics Plasma applications Oxidation Hafnium Nitrogen Plasma properties Plasma materials processing Plasma stability CMOS process

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Hydrodynamik und Stofftransport in einer Miniplant‐Extraktionskolonne

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Chemie Ingenieur Technik 2003年第8期75卷 1166-1167页

作者： P. Kolb H.‐J. Bart U. Bühlmann B. Schenkel J. Jeisy C. rose Lehrstuhl für Thermische Verfahrenstechnik Universität Kaiserslauter Kühni AG Verfahrenstechnik und Umwelttechnik Allschwil Schweiz Novartis Pharma AG Technical R&D Basel Schweiz Roche AG Process Development Sisseln Schweiz Lonza AG Visp Schweiz.

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Examination and improvement of reading disturb characteristics of a surrounded gate STTM memory cell

Examination and improvement of reading disturb characteristi...

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IEEE Conference on Nanotechnology

作者： S.J. Ahn K.H. Koh K.W. Kwon S.J. Baek Y.N. Hwang G.T. Jung H.S. Jung K. Kim Semiconductor R&D center Device Solution Network Samsung Electronics Company Limited Yongin si Gyeonggi South Korea DRAM Design Team Semiconductor R&D center Device Solution Network Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Process Development Team Semiconductor R&D center Device Solution Network Samsung Electronics Company Limited Yongin si Gyeonggi South Korea

This paper introduces a novel surrounded gate STTM cell technology to improve retention and read disturb characteristics. In the memory cells previously reported, the device structures limits the CMOS-compatible memory integration and the operation voltage scaling of the memory cells. The proposed cell architecture overcomes this problem and also improves the read disturb characteristics. The proposed memory cell was fabricated using the 0.18 um design rule based on the low power SrAM process technology. This paper demonstrate an the device characteristics of the proposed memory cell and the improvement of tin a read disturb characteristics.

关键词： Capacitance Voltage random access memory Writing CMOS technology Transistors Nonvolatile memory process design research and development Consumer electronics

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Phase-change chalcogenide nonvolatile rAM completely based on CMOS technology

Phase-change chalcogenide nonvolatile RAM completely based o...

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International Symposium on VLSI Technology, Systems and Applications

作者： Y.N. Hwang J.S. Hong S.H. Lee S.J. Ahn G.T. Jeong G.H. Koh H.J. Kim W.C. Jeong S.Y. Lee J.H. Park K.C. ryoo H. Horii Y.H. Ha J.H. Yi W.Y. Cho Y.T. Kim K.H. Lee S.H. Joo S.O. Park U.I. Jeong H.S. Jeong Kinam Kim Advanced Technology Development Semiconductor R&D Division Samsung Electronics Company Limited Yongin si Kyunggi South Korea Process Development Samsung Electronics Company Limited Yongin si Kyunggi South Korea Process Development Samsung Electronics Co. Ltd Yongin Korea Computer Aided Engineering Teams Samsung Electronics Co. Ltd Yongin Korea

ISBN: (纸本)0780377656

We have integrated a phase-change chalcogenide random access memory, completely based on 0.24 /spl mu/m-CMOS technologies. A twin cell and BL clamping circuits are introduced to enlarge fabrication tolerance and to reduce cell perturbation during reading operation. To draw back current as much as possible, Co salicidation is also applied to transistor formation. By constructing a simple cell structure with Ge/sub 2/Sb/sub 2/Te/sub 5/, we have observed reliable phase-transitions by driving current through MOS transistors. With 100 ns-writing pulses of 2 mA for rESET and 0.6 mA for SET, the device operates successfully with a considerable sensing signal at reading voltage of as low as 0.2 V.

关键词： CMOS technology Integrated circuit technology Nonvolatile memory read-write memory random access memory Clamps Fabrication Tellurium MOSFETs Low voltage

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Highly scalable and CMOS-compatible STTM cell technology

Highly scalable and CMOS-compatible STTM cell technology

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International Electron devices Meeting (IEdM)

作者： S.J. Ahn G.H. Koh K.W. Kwon S.J. Baik G.T. Jung Y.N. Hwang H.S. Jeong Kinam Kim Advanced Technology Develoument Device Solution Network Samsung Electronics Company Limited Yongin si Gyeonggi South Korea DRAM Desien 3 Device Solution Network Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Process Develooment Semiconductor R&D Center Device Solution Network Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Advanced Technology Development Device Solution Network Samsung Electronics Co.LTD Yongin-City Kyunggi-Do Korea

The technological challenges associated with STTM (scalable two transistor memory) cells were reviewed. First of all, the basic operating principles of the memory cell are discussed. This is followed by the introduction of the memory array formation and co-process of the I/O transistor, applying a 0.24 /spl mu/m design rule test vehicle. A new cell structure of a surrounded gate STTM structure is introduced. In addition, the process technology and the performance of the memory cell are presented.

关键词： CMOS technology Threshold voltage random access memory Transistors Flash memory Boron Writing Electrons research and development Testing

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Test circuits for fast and reliable assessment of CdM robustness of I/O stages

Test circuits for fast and reliable assessment of CDM robust...

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Electrical Overstress/Electrostatic discharge Symposium (EOS/ESd)

作者： W. Stadler K. Esmark K. reynders M. Zubeidat M. Graf W. Wilkening J. Willemen N. Qu S. Mettler M. Etherton d. Nuernbergk H. Wolf H. Gieser W. Soppa V. de Heyn M. Natarajan G. Groeseneken E. Morena r. Stella A. Andreini M. Litzenberger d. Pogany E. Gornik C. Foss A. Konrad M. Frank European MEDEA+ ASDESE (Application Specific Design for ESD and Substrate Effects) Cooperation CL DAT LIB IO Infineon Technologies Munich Germany AMI Semiconductors Inc. Oudenaarde Belgium Atmel Germany GmbH Heilbronn Germany Robert Bosch GmbH AE/DICI Reutlingen Germany European MEDEA+ ASDESE (Application Specific Design for ESD and Substrate Effects) Cooperation Erfurt Germany IZM Fraunhofer-Institut Zuverlaessigkeit und Mikrointegration ATIS Munich Germany FH Osnabrück FB Elektrotechnik Osnabrück Germany IMEC Leuven Belgium STMicroelectronics TPA R&D - BCD Process Development Cornaredo (MI) Italy Institute for Solid State Electronics (ISSE) Vienna University of Technology Vienna Austria TPA RD-BCD Process Development STMicroelectronics Cornaredo Italy

CdM hardening during the development of technology, devices, libraries and finally products differs significantly from the process well-established for HBM. This paper introduces a method on the basis of specialized CdM test structures including protection elements and sensitive monitor elements. These test structures mimic typical CdM-sensitive circuits found by physical failure analysis over the years. Manufactured in five different technologies, structures were assembled in both a regular package and a new package emulator. CdM stress tests, vf-TLP tests, backside laser interferometry, device simulation, and failure analysis lead to new insights in the complex interdependencies during CdM and underline the need of CdM-specific test structures.

关键词： Circuit testing robustness Failure analysis Packaging Libraries Protection Condition monitoring Manufacturing Assembly Stress

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process integration of Cu metallization and ultra low k (k=2.2)

Process integration of Cu metallization and ultra low k (k=2...

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IEEE International Conference on Interconnect Technology

作者： Chuan-cheng Cheng Wei-jen Hsia J. Pallinti S. Neumann J. Koh P. Li Mei Zhu M. Lu Hao Cui T. Fujimoto W. Catabay P. Wright Process Technology Department. Process R&D LSI Logic Corporation Santa Clara CA USA Process Module Development and Advance Research LSI Logic Corporation Gresham OR USA

The first process integration of Cu metallization and next generation CVd ultra low k (Trikon Orion ULK, k=2.2) is presented. The current process condition for a 130 nm node Cu/lowk (k=2.9) process is applied to Cu/ULK and found to be suitable without major modifications. The comparison of post CMP measurement (dishing, erosion, peeling, and scratch) show no significant variation between control (k=2.9) and ULK. The electrical data indicates the successful integration of Cu and ULK. The interconnect capacitance is expected to reduce 20% at 0.1 /spl mu/m technology node using the ULK film.

关键词： Metallization Etching Silicon carbide Chemistry Large scale integration Logic delay dielectric materials dielectric constant Inspection

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Highly manufacturable sub-100 nm drAM integrated with full functionality

Highly manufacturable sub-100 nm DRAM integrated with full f...

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Symposium on VLSI Technology

作者： S. Choi B.Y. Nam J.-H. Ku d.C. Kim S.H. Lee J.J. Lee J.W. Lee J.d. ryu S.J. Heo J.K. Cho S.P. Yoon C.J. Choi Y.J. Lee J.H. Chung B.H. Kim M.B. Lee G.H. Choi Y.S. Kim K. Fujihara U.I. Chung J.T. Moon Process Development Team Semiconductor R&D Division Samsung Electronics Company Limited Yongin si Kyunggi South Korea

ISBN: (纸本)078037312X

Sub-100 nm drAM is successfully fabricated for the first time with several key technologies, including W/W/sub x/N-poly gate, bitline structure having low parasitic capacitance, ru/Ta/sub 2/O/sub 5//poly-Si capacitor and advanced CVd-Al contact processes. A fully functional working device is obtained with promising cell performance. Each technology also shows its extendibility as a manufacturable module process for further scaled drAM.

关键词： Manufacturing random access memory Capacitance Capacitors Tin Space technology Temperature Surface treatment Transistors Moon

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Highly reliable interconnect technology featuring 90 nm drAM integration

Highly reliable interconnect technology featuring 90 nm DRAM...

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IEEE International Conference on Interconnect Technology

作者： U-In Chung Siyoung Choi Gil-Heyun Choi Process Development Team Semiconductor R&D Division Samsung Electronics Company Limited Yongin si Kyunggi South Korea

reliable interconnection with low resistance is substantially required on drAM with 90 nm design rule in terms of its integration and functionality. Several key interconnect technologies, including poly metal gate, W bitline, contact and via processes using advanced CVd-Al, are described. Full metal interconnected drAM exhibits excellent performance and even further scalability.

关键词： random access memory Filling Thermal resistance Scalability Contact resistance Substrates Capacitors research and development Etching Home appliances

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