检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

118 篇 会议
108 篇 期刊文献

馆藏范围

226 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

106 篇 工学
- 34 篇 电子科学与技术（可...
- 34 篇 化学工程与技术
- 21 篇 材料科学与工程（可...
- 12 篇 电气工程
- 12 篇 计算机科学与技术...
- 9 篇 机械工程
- 8 篇 动力工程及工程热...
- 8 篇 土木工程
- 7 篇 冶金工程
- 7 篇 船舶与海洋工程
- 4 篇 力学（可授工学、理...
- 4 篇 信息与通信工程
- 4 篇 矿业工程
- 3 篇 石油与天然气工程
- 3 篇 轻工技术与工程
- 3 篇 交通运输工程
- 3 篇 环境科学与工程（可...
- 3 篇 软件工程
- 3 篇 安全科学与工程
51 篇 理学
- 28 篇 化学
- 17 篇 物理学
- 7 篇 数学
- 7 篇 生物学
- 5 篇 海洋科学
9 篇 管理学
- 9 篇 管理科学与工程(可...
- 3 篇 工商管理
8 篇 医学
- 5 篇 基础医学(可授医学...
- 3 篇 临床医学
- 3 篇 药学(可授医学、理...
4 篇 农学
2 篇 经济学
- 2 篇 应用经济学
1 篇 法学
1 篇 军事学

主题

28 篇 random access me...
24 篇 research and dev...
16 篇 capacitance
15 篇 electrodes
15 篇 capacitors
14 篇 leakage current
13 篇 tin
12 篇 etching
12 篇 cmos technology
11 篇 moon
11 篇 degradation
10 篇 fabrication
10 篇 transistors
10 篇 silicon
9 篇 threshold voltag...
9 篇 substrates
8 篇 scalability
8 篇 contact resistan...
8 篇 voltage
8 篇 annealing

机构

7 篇 process developm...
5 篇 dupont co. exper...
5 篇 research center ...
5 篇 department of ch...
5 篇 school of petroc...
5 篇 department of ch...
5 篇 api r&d ipdo dr....
5 篇 shandong ultra-d...
5 篇 department of ch...
5 篇 key laboratory o...
5 篇 chemical process...
4 篇 process developm...
4 篇 process developm...
3 篇 pharmaceuticals ...
3 篇 chemical process...
3 篇 process developm...
3 篇 chemical & analy...
3 篇 r&d global cmc d...
3 篇 samsung electron...
3 篇 global cmc devel...

作者

12 篇 joo-tae moon
11 篇 kinam kim
8 篇 u-in chung
8 篇 ho-kyu kang
7 篇 sang in lee
6 篇 chang-ki hong
6 篇 y.n. hwang
6 篇 h.s. jeong
6 篇 s.h. lee
6 篇 h.j. kim
5 篇 de bettencourt-d...
5 篇 shi feng
5 篇 eastgate martin ...
5 篇 j.t. moon
5 篇 g.t. jeong
5 篇 g.h. koh
5 篇 bandichhor rakes...
5 篇 radu nora s.
5 篇 s.j. ahn
5 篇 borovik a. s.

语言

216 篇 英文
6 篇 其他
2 篇 中文

检索条件"机构=R&D Process Development"

共 226 条记录，以下是181-190 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

A new ALd-TiN/CoSi/sub 2/ contact plug process for reliable and low defect density bit-line integration in sub-quarter micron giga-bit drAM

A new ALD-TiN/CoSi/sub 2/ contact plug process for reliable ...

引用

IEEE International Conference on Interconnect Technology

作者： Seong Geon Park Sang-Bom Kang Gil Heyun Choi U In Chung Joo Tae Moon Process Development Team 2 Semiconductor R&D Center Samsung Electronics Company Limited Yongin si Kyunggi South Korea

This paper reports a new ALd-TiN/CoSi/sub 2/ contact plug process for giga-bit scale drAM bit-line contacts. Using this technology, we obtained a low contact resistance of 315/spl Omega//cnt for BL/N+ and 1518/spl Omega//cnt for BL/P+ in 0.16 /spl mu/m contacts, as well as a crack-free integration scheme and low level of defect density.

关键词： Plugs Tin Heat treatment Etching Impurities Contact resistance displays Thermal resistance Materials testing Hydrogen

来源：评论

学校读者我要写书评

暂无评论

Characterization of multi-barrier tunneling diodes and vertical transistors using 2-d device simulation

引用

International Conference on Simulation of Semiconductor processes and devices (SISPAd)

作者： Kwan-do Kim Keun-Ho Lee Seung-Jae Baik Jun-Ha Lee Tai-Kyung Kim Jeong-Taek Kong CAE Team Canada Process Development Team Semiconductor R&D Center Samsung Electronics Company Limited Yongin si Gyeonggi South Korea

ISBN: (纸本)4891140275

A novel memory cell which adopts a floating gate device with the writing mechanism of direct tunneling through the multiple tunnel junction(MTJ) was proposed recently. The device is known to have potential advantages of scalability, high density, high speed, long data retention time, low voltage operation, low power consumption and good endurability. Characterization and optimization of the vertical transistor with MTJ enables the construction of a novel high-density memory with high speed writing and long data retention time. This paper presents a numerical analysis of the tunnel barriers in explaining I-V characteristics of the vertical transistor. We have characterized the vertical transistor with double and triple barriers from the point of view of the central barrier. We have also performed extensive 2-d device simulation for multi barrier tunneling diodes and vertical transistors with various device parameters. results of the present analysis are expected to provide guidelines for designing the experiments for optimal transistor fabrications.

关键词： diodes Nonvolatile memory Writing Scalability Low voltage Energy consumption Magnetic tunneling Numerical analysis Guidelines Fabrication

来源：评论

学校读者我要写书评

暂无评论

A novel robust TiN/AHO/TiN capacitor and CoSi/sub 2/ cell pad structure for 70nm stand-alone and embedded drAM technology and beyond

A novel robust TiN/AHO/TiN capacitor and CoSi/sub 2/ cell pa...

引用

International Electron devices Meeting (IEdM)

作者： J.M. Park Y.S. Hwang d.S. Hwang H.K. Hwang S.H. Lee G.Y. Kim M.Y. Jeong B.J. Park S.E. Kim M.H. Cho d.I. Kim J.-H. Chung I.S. Park C.-Y. Yoo J.H. Lee B.Y. Nam Y.r. Park C.-S. Kim M.-C. Sun J.-H. Ku S. Choi H.S. Kim Y.G. Park Kinam Kim Advanced Technology Development Yongin si South Korea Advanced Technology Development Process Development Semiconductor Research and Development Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Process Development Semiconductor R&D Div. Samsung Electronics Co. Kiheung-Eup Yongin-City Kyunggi-Do Korea

For the first time, a novel robust (square-shape cylinder type) TiN/AHO (Al/sub 2/O/sub 3/-HfO/sub 2/)/TiN capacitor with Co-silicide on landing cell pad suitable for both stand-alone and embedded drAMs are successfully developed with 88nm (pitch 176nm) feature size, which is the smallest feature size ever reported in drAM technology, using ArF lithography for aiming 70nm stand-alone and embedded drAM technology. The capacitor with Toxeq of 1.5nm and leakage current of less than 1 fA/cell is achieved. The cell contact resistance is greatly improved by using Co-silicidation on landing cell pad and metal storage node contact plug, which results in high performance.

关键词： Tin robustness Atherosclerosis random access memory Contact resistance Plugs MIM capacitors Leakage current Capacitance robust stability

来源：评论

学校读者我要写书评

暂无评论

Effects of nitrogen in HfSiON gate dielectric on the electrical and thermal characteristics

Effects of nitrogen in HfSiON gate dielectric on the electri...

引用

International Electron devices Meeting (IEdM)

作者： M. Koyama A. Kaneko T. Ino M. Koike Y. Kamata r. Iijima Y. Kamimuta A. Takashima M. Suzuki C. Hongo S. Inumiya M. Takayanagi A. Nishiyama Advanced LSI Technology Laboratory Advanced LSI Technology Laboratory Toshiba Corporation Yokohama Japan Environmental Engineering and Analysis Center R&D Center Toshiba Corporation Yokohama Japan Environmental Engineering and Analysis Center R&D Center Toshiba Corporation Process & Manufacturing Engineering Center SoC Research & Development Center Semiconductor Company Toshiba Corporation Yokohama Japan SoC Research Development Center Semiconductor Company Toshiba Corporation Yokohama Japan

The effects of the nitrogen in the HfSiON gate dielectric on the electrical and thermal properties of the dielectric were investigated. It is clearly demonstrated that nitrogen enhances the dielectric constant of silicates. High dielectric constants of the HfSiON are maintained and boron penetration is substantially suppressed in the HfSiON during high temperature annealing. These properties are ascribed to the homogeneity of the bond structure in the film containing nitrogen through high temperature annealing.

关键词： Nitrogen dielectric constant Temperature Bonding Annealing High-K gate dielectrics Thermal stability Polarization Boron High K dielectric materials

来源：评论

学校读者我要写书评

暂无评论

Void free and low stress shallow trench isolation technology using P-SOG for sub 0.1 /spl mu/m device

Void free and low stress shallow trench isolation technology...

引用

Symposium on VLSI Technology

作者： Jin-Hwa Heo Soo-Jin Hong dong-Ho Ahn Hyun-duk Cho Moon-Han Park K. Fujihara U-In Chung Yong-Chul Oh Joo-Tae Moon Semiconductor R&D Center Samsung Electronics Co. Ltd. Yongin-City Kyungki-Do Korea Semiconductor R& 11 Center Samsung Electronics Company Limited Yongin si Kyunggi South Korea Process Development Team TD Yongin-City Kyungki-Do Korea

ISBN: (纸本)078037312X

Highly reliable void free shallow trench isolation (VF-STI) technology by employing polysilazane based inorganic spin-on-glass (P-SOG) is developed for sub-0.1 /spl mu/m devices. In order to overcome the difficulties from the gap-filling and accumulated mechanical stress in STI, a P-SOG pillar is introduced at the trench bottom. As a result, the P-SOG pillar, having low stress, improves data retention time and hot carrier immunity in 256 Mbit drAM by reducing cumulative STI stress. In addition, VF-STI shows an excellent extendibility in terms of gap filling capability even at an aspect ratio of more than 10 without void formation.

关键词： Isolation technology Voltage Annealing Hot carriers Paper technology Compressive stress Temperature measurement degradation Leakage current Probability distribution

来源：评论

学校读者我要写书评

暂无评论

drAM scaling-down to 0.1 /spl mu/m generation using bitline spacerless storage node SAC and rIr capacitor with TiN contact plug

DRAM scaling-down to 0.1 /spl mu/m generation using bitline ...

引用

Symposium on VLSI Technology

作者： Beom-Jun Jin Young-Pil Kim Byeong-Yun Nam Hyoung-Joon Kim Young-Wook Park Joo-Tae Moon Process Development Team Semiconductor R&D Center Samsung Electronics Company Limited South Korea

ISBN: (纸本)4891140127

As drAM downscaling approaches the 0.1 /spl mu/m generation, problems related to transistor short channel effects, storage capacitance, gap filling of high aspect ratio patterns, and leakage currents through each module must be solved. Among these, processing around the storage node self-aligned contact (SAC) is the most critical problem for integration of capacitor-on-bitline (COB) drAM devices because it is one of the deepest contacts with high aspect ratio; and it reaches the cell transistor junction. However, few reports have addressed this issue, while others have been reported elsewhere (Song et al., 2000; Jeong et al., 2000; Won et al., 2000; Kim et al., 2000). In this paper, a novel process of bitline spacerless storage node SAC and ru-Ta/sub 2/O/sub 5/-ru (rIr) capacitor with TiN contact plug is studied for the integration of 0.1 /spl mu/m design-rule based drAMs. It was found that the spacerless SAC process made downscaling to the 0.1 /spl mu/m design-rule possible and also that it has better electrical properties than the conventional SAC.

关键词： random access memory Contact resistance Tin Capacitors Plugs Etching Material storage Leakage current Filling Insulation

来源：评论

学校读者我要写书评

暂无评论

Ge-redistributed poly-Si/SiGe stack gate (GrPSG) for high-performance CMOSFETs

Ge-redistributed poly-Si/SiGe stack gate (GRPSG) for high-pe...

引用

Symposium on VLSI Technology

作者： H.S. rhee G.J. Bae T.H. Choe S.S. Kim S. Song N.I. Lee K. Fujihara H.K. Kang J.T. Moon Process Development Team Semiconductor R&D Division Samsung Electronics Company Limited Yongin si South Korea

ISBN: (纸本)4891140127

A Ge-redistributed poly-Si/SiGe stack gate (GrPSG) has been proposed to improve the current performance of PMOS without the degradation of NMOS for sub-0.1 /spl mu/m CMOSFETs with ultrathin gate oxide. Ge diffusion into the poly-Si layer was promoted more by ion implantation of N-type dopants such as P and As rather than P-type dopants. NMOS and PMOS had different Ge concentrations at the interface between gate electrode and gate oxide by an additional anneal to redistribute the Ge profile. The current performance of NMOS with GrPSG with low Ge content (<5%) was not degraded, while that of PMOS with GrPSG with high Ge content (>20%) was improved due to suppression of the poly-depletion effect and boron penetration. In addition, the gate reoxidation was modified to reduce G/sub m/ degradation by reduced gate bird's beak. High-performance 70 nm-CMOSFETs were successfully fabricated using the simple GrPSG process.

关键词： Silicon germanium Germanium silicon alloys CMOSFETs MOS devices degradation Annealing Boron Ion implantation CMOS technology Moon

来源：评论

学校读者我要写书评

暂无评论

Electromigration reliability of dual damascene copper interconnect with different IMd structures

Electromigration reliability of dual damascene copper interc...

引用

IEEE International Conference on Interconnect Technology

作者： Young-Jin Wee Ki-Chul Park Won-Sang Song Hyeon-deok Lee Wo-Kyu Kang Joo-Tae Moon Process Development Team Semiconductor R&D Center Samsung Electronics Company Limited Yongin si Gyeonggi South Korea

ISBN: (纸本)0780366786

Electromigration behavior of dual damascene Cu interconnect has been investigated comparing PE-TEOS SiO/sub 2/ with fluorine doped SiO/sub 2/ (FSG). MTFs of FSG in both line and contact EM tests were significantly shorter than those of PE-TEOS. The higher compressive stress and fluorine of FSG dielectric are considered to affect the EM reliability performance of the confined Cu interconnect.

关键词： Electromigration Copper Testing Heating Wiring Thermal conductivity Adhesives Stress dielectric materials dry etching

来源：评论

学校读者我要写书评

暂无评论

Backend process for Cylindrical ru/Ta2O5/ru Capacitor for Future drAM

Backend Process for Cylindrical Ru/Ta2O5/Ru Capacitor for Fu...

引用

2001 6～(th) International Conference on Solid-State and Integrated Circuit Technology

作者： J.Lin T.Suzuki H.Minakata A.Shimada K.Tsunoda M.Fukuda T.Kurahashi Y.Fukuzumi A.Hatada A.Sato P.H.Sun Y.Ishibashi H.Tomita N.Nishikawa E.Ito W.C.Liu C.M.Chu r.Suzuki M.Nakabayashi d.Matsunaga K.Hieda K.Hashimoto S.Nakamura Y.Kohyama C.M.Shiah Technology Development Division Fujitsu Limited Technology Development Division Fujitsu Limited Fujitsu Laboratories Limited Technology Development Division Fujitsu Limited Fujitsu Laboratories Limited Fujitsu Laboratories Limited Fujitsu Laboratories Limited Memory LSI R&D Center Toshiba Corporation Fujitsu Laboratories Limited Fujitsu Laboratories Limited DRAM Process Integration and Module Technology Department Winbond Electronics Corporation Memory LSI R&D Center Toshiba Corporation Process&Manufacturing Engineering Center Toshiba Corporation Technology Development Division Fujitsu Limited Process&Manufacturing Engineering Center Toshiba Corporation DRAM Process Integration and Module Technology Department Winbond Electronics Corporation DRAM Process Integration and Module Technology Department Winbond Electronics Corporation Fujitsu Laboratories Limited Technology Development Division Fujitsu Limited Technology Development Division Fujitsu Limited Process&Manufacturing Engineering Center Toshiba Corporation Technology Development Division Fujitsu Limited Fujitsu Laboratories Limited Memory LSI R&D Center Toshiba Corporation DRAM Process Integration and Module Technology Department Winbond Electronics Corporation

A novel backend process is developed for thecylindrical ru/TaO/ru capacitor for 130nm generationdrAMs to achieve good electrical *** gas（3%H/97%N）anneal（FGA） induceddegradation can be effectively *** thecylindrical ru/TaO/ru capacitor with full backendprocesses,including passivation layer formation and aFGA,the cell leakage current and cell capacitance are1fA（at±0.8V at 85℃）and 15fF,respectively.

关键词： Backend process for Cylindrical ru/Ta2O5/ru Capacitor for Future drAM FGA

来源：评论

学校读者我要写书评

暂无评论

Highly reliable interconnect integration of Cu and low-k organic polymer based on fine Cd controls

Highly reliable interconnect integration of Cu and low-k org...

引用

IEEE International Conference on Interconnect Technology

作者： Y. Nishioka S. Tomohisa Y. Toyoda T. Fukada T. Satake M. Matsuura S. domae A. Ohsaki ULSI Development Center Mitsubishi Electric Corporation Limited Itami Hyogo Japan Advanced Technology R&D Center Mitsubishi Electric Corporation Limited Amagasaki Hyogo Japan ULSI Process Technology Development Center Matsushita Electronics Corporation Kyoto Japan

ISBN: (纸本)0780366786

A Cu dual damascene interconnect with a low-k organic polymer was fabricated and Cd changes of its vias and trenches were investigated. By means of optimizing both the SiO/sub 2/ etching condition and the SiN thickness in a stacked hard mask, Cd changes of trenches from a designed pattern size to the final one were suppressed up to about 10 nm. As a result, electrical properties were controlled and kept close to calculated values from the designed pattern size. This synthetic process integration based on the fine Cd control technique is promising for the realization of a fine dual damascene interconnect of 0.13-/spl mu/m and further technology node.

关键词： Etching Silicon compounds Ultra large scale integration dielectric materials Fabrication Polymer films Size measurement resists research and development design optimization

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共23页 << < 14 15 16 17 18 19 20 21 22 23 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：