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检索条件"机构=R&D Process Development"

共 226 条记录，以下是191-200 订阅

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A noble metallization process using Preferential Metal deposition (PMd)-aluminum with methylpyrroridine alane (MPA)

A noble metallization process using Preferential Metal Depos...

引用

IEEE International Conference on Interconnect Technology

作者： Jong Myeong Lee Byung Hee Kim Ju Young Yun Myoung Bum Lee Gil Heyun Choi Young Wook Park Hyun Koock Shin Sang In Lee Joo Tae Moon Process Development Team Samsung Electronics Co. Ltd Yongin-City Kyungki-Do KOREA Process Development Team Semiconductor R&D Center Samsung Electronics Company Limited Yongin si Gyeonggi South Korea UP Chemical Co. Pyongtaek-City Kyungki-Do KOREA UP Chemical Company Limited Pyeongtaek Gyeonggi South Korea

ISBN: (纸本)0780366786

A noble Al precursor of methylpyrooridine alane (MPA) showed excellent stabilities and lifetime compared to any other Al precursor. The preferential Metal deposition (PMd)-Al, which used a CVd-Al process with MPA, showed excellent contact fill and electrical properties, which implied that PMd-Al using MPA can be applied to a ULSI drAM metallization process, such as metal contact and via holes.

关键词： Metallization Optical films Surface morphology Chemicals Bonding Stability Contacts random access memory Temperature sensors Substrates

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Backend process for cylindrical ru/Ta/sub 2/O/sub 5//ru capacitor for future drAM

Backend process for cylindrical Ru/Ta/sub 2/O/sub 5//Ru capa...

引用

International Conference on Solid-State and Integrated Circuit Technology

作者： J. Lin T. Suzuki H. Minakata A. Shimada K. Tsunoda M. Fukuda T. Kurahashi Y. Fukuzumi A. Hatada A. Sato P.H. Sun Y. Ishibashi H. Tomita N. Nishikawa E. Ito W.C. Liu C.M. Chu r. Suzuki M. Nakabayashi d. Matsunaga K. Hieda K. Hashimoto S. Nakamura Y. Kohyama C.M. Shiah Technology Development Division Fujitsu Laboratories Limited Yokohama Japan Fujitsu Laboratories Limited Yokohama Japan Memory LSI R&D Center Toshiba Corporation Yokohama Japan DRAM Process Integration and Module Technology Department Winbond Electronics Corporation Yokohama Japan Process&Manufactg Engineering Center Toshiba Corporation Yokohama Japan

ISBN: (纸本)0780365208

A novel backend process is developed for the cylindrical ru/Ta/sub 2/O/sub 5//ru capacitor for 130 nm generation drAMs to achieve good electrical characteristics. Forming gas (3%H/sub 2//97%N/sub 2/) anneal (FGA) induced degradation can be effectively suppressed. For the cylindrical ru/Ta/sub 2/O/sub 5//ru capacitor with full backend processes, including passivation layer formation and a FGA, the cell leakage current and cell capacitance are 1 fA (at /spl plusmn/0.8 V at 85/spl deg/C) and 15fF, respectively.

关键词： Capacitors random access memory Tin resists Surface contamination Cleaning Fabrication Lithography Mass spectroscopy Etching

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A 99-mm/sup 2/, 0.7-W, single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mbit embedded drAM for portable 422P@HL encoder system

A 99-mm/sup 2/, 0.7-W, single-chip MPEG-2 422P@ML video, aud...

引用

Custom Integrated Circuits Conference (CICC)

作者： S. Kumaki H. Takata Y. Ajioka T. Ooishi K. Ishihara A. Hanami T. Tsuji Y. Kanehira T. Watanabe C. Morishima T. Yoshizawa H. Sato S. Hattori A. Koshio K. Tsukamoto T. Matsumura System LSI Development Center Mitsubishi Electric Corporation Limited Japan System LSI Division Mitsubishi Electric Corporation Limited Japan ULSI Development Center Mitsubishi Electric Corporation Limited Itami Hyogo Japan Information Technology R&D Center Mitsubishi Electric Corporation Limited Kamakura Kanagawa Japan ULSI Process Technology Development Center Semiconductor Company Matsushita Electronics Corporation Kyoto Japan

ISBN: (纸本)0780365917

A scalable single-chip 422P@ML MPEG-2 video, audio, and system encoder LSI for portable 422P@HL system is described. The encoder LSI is implemented using 0.13 /spl mu/m embedded drAM technology. It integrates 3-M logic gates and 64-Mbit drAM in an area of 99-mm/sup 2/. The power consumption is suppressed to 0.7-Watts by adopting a low power drAM core. It performs real-time 422P@ML video encoding, audio encoding, and system encoding with no external drAM. Furthermore, the encoder LSI realizes a 422P@HL video encoder with multi-chip configuration, due to its scalable architecture. This results in a PC-card size 422P@HL encoder with lowest power consumption for portable HdTV codec system.

关键词： random access memory Encoding Large scale integration HdTV digital filters Nonlinear filters Ultra large scale integration Energy consumption real time systems Costs

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development of CVd-ru/Ta/sub 2/O/sub 5//CVd-TiN capacitor for multigigabit-scale drAM generation

Development of CVD-Ru/Ta/sub 2/O/sub 5//CVD-TiN capacitor fo...

引用

Symposium on VLSI Technology

作者： Wan don Kim Jin Won Kim Seok Jun Won Sang don Nam Byeong Yun Nam Cha Young Yoo Young Wook Park Sang In Lee Moon Yong Lee Process Development Team Semiconductor R&D Center Samsung Electronics Company Limited South Korea

ISBN: (纸本)0780363051

We have investigated the electrical properties of metal/Ta/sub 2/O/sub 5//metal (MIM-Ta/sub 2/O/sub 5/) capacitor for multigigabit-scale drAMs. CVd-TiN film was used as a bottom electrode, whereas PVd-TiN, CVd-TiN and CVd-ru metals were compared for a top electrode. Our results, including electrical properties and step coverage, showed that a CVd-ru film is the most promising top electrode material. Based on this result, a CVd-ru/Ta/sub 2/O/sub 5//CVd-TiN capacitor with cylinder-type storage node was developed, and the cell capacitance of 40fF/cell with the leakage current of 0.1fA/cell at /spl plusmn/1 V applied voltage was accomplished.

关键词： Capacitors random access memory Electrodes Tin Semiconductor films Annealing Leakage current Voltage Gases dielectric constant

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Novel MIS Al/sub 2/O/sub 3/ capacitor as a prospective technology for Gbit drAMs

Novel MIS Al/sub 2/O/sub 3/ capacitor as a prospective techn...

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Symposium on VLSI Technology

作者： In-Sung Park Byoung Taek Lee Sung Je Choi Jae Soon Im Seung Hwan Lee Ki Yeon Park Joo Won Lee Yong Woo Hyung Yeong Kwan Kim Heung Soo Park Young Wook Park Sang In Lee Moon Yong Lee Process Development Team Semiconductor R&D Division Samsung Electronics Company Limited Yongin si South Korea

ISBN: (纸本)0780363051

A novel MIS-Al/sub 2/O/sub 3/ capacitor technology was developed with the low thermal budget and showed the superior dielectric characteristics, which were achieved by adopting ALd technique for the Al/sub 2/O/sub 3/ film deposition. A fully integrated 1 Gbit drAM with MIS-Al/sub 2/O/sub 3/ capacitor was successfully worked, where storage capacitance and leakage current at 1.2 V were 30 fF/cell and 0.5 fA/cell, respectively. Moreover, the excellent dielectric characteristics were confirmed from the result that Vp for generating solid "0" 10 sec fail bit counts was measured to be 2.4 V.

关键词： Capacitors random access memory Electrodes Capacitance Leakage current Solids dielectric measurements Tin Character generation Thermal resistance

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Feasibility of new ArC using PECVd for both KrF and ArF lithography

Feasibility of new ARC using PECVD for both KrF and ArF lith...

引用

International Conference on Microprocesses and Nanotechnology

作者： Yongbeom Kim Junghyeon Lee Hanku Cho Jootae Moon Process Development Team Semiconductor R&D Samsung Electronics Company Limited Yongin si Kyunggi South Korea

ISBN: (纸本)4891140046

We developed and confirmed the feasibility of a new carbon ArC (CArC) for both KrF and ArF lithography. CArC has high conformability on topography and is easily removable during the resist stripping process. Also good ArC performance and etch characteristics of CArC with sublayers are obtained. Thus, CArC is a promising alternative to SiON ArC and organic ArC.

关键词： Lithography Etching reflectivity Carbon Hydrogen Chemical elements Organic materials Optical refraction Extinction coefficients Substrates

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Formation of sub-100 nm contact hole patterns using a novel resist material

Formation of sub-100 nm contact hole patterns using a novel ...

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International Conference on Microprocesses and Nanotechnology

作者： Sang-Jun Choi Yool Kang Jeong-Hee Chung Sang-Gyun Woo Joo-Tae Moon Process Development Team Semiconductor R&D Division Samsung Electronics Company Limited Yongin si South Korea

ISBN: (纸本)4891140046

Flow process using a novel resist called the SMArT (Samsung Advanced resist for Thermal flow process) was studied. The SMArT consisted of conventional polyhydroxy styrene-based polymers and the additives for cross-linking reactions with base polymers. When the SMArT was used, 240 nm contact hole patterns were reduced to 90 nm final patterns without much pattern deformation. At 90 nm resolution, the critical dimension (Cd) uniformity on 200 mm wafer was less than 20 nm. The etching selectivity of resist to silicon oxide was increased due to the cross-linking reaction. Based on these results, the flow process by the SMArT is a very promising candidate for the fabrication of gigabit devices.

关键词： resists Silicon Lithography Image motion analysis Etching Semiconductor materials Moon research and development Optical device fabrication Costs

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The drive currents improvement of FdSOI MOSFETs with undoped Si epitaxial channel and elevated source/drain structure

The drive currents improvement of FDSOI MOSFETs with undoped...

引用

IEEE SOI-3d-Subthreshold Microelectronics Technology Unified Conference (S3S)

作者： Sang-Su Kim Tae-Hee Choe Hwa-Sung rhee Geum-Jong Bae Kyung-Wook Lee Nae-In Lee K. Fujihara Ho-Kyu Kang Ju-Tae Moon Center for Semicond. R&D Samsung Electron. Co. Ltd. Kyunggi-do South Korea Process Development Team Semiconductor R&D Center Samsung Electronics Company Limited Yongin si South Korea

Fully-depleted silicon-on-insulator (FdSOI) MOSFETs are very attractive for low-voltage applications due to ideal subthreshold slope, short channel effect (SCE) immunity and reduced junction capacitance compared to bulk silicon MOSFETs. However, the channel mobility degradation due to higher channel doping for threshold voltage (V/sub th/) adjustment and higher source-drain resistance (r/sub sd/) are critical issues for FdSOI MOSFETs with top silicon thickness of less than 50 nm (Wong et al, 1998; Su et al, 1993). It has been reported that an undoped Si epitaxial channel (UEC) of the bulk MOSFETs and elevated source/drain (E-S/d) structures of the FdSOI MOSFETs are very effective for improvement of channel mobility and a low r/sub sd/, respectively (Yan et al, 1992; Kircher et al., 1992; Cao et al., 1997). In this paper, we propose the implementation of UEC for only nMOSFETs and the E-S/d structure for both n- and pMOSFETs to improve drive currents.

关键词： MOSFETs MOS devices degradation Moon research and development Silicon on insulator technology Capacitance doping Threshold voltage Ion implantation

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Charge trapping mechanism under dynamic stress and its effect on failure time [gate oxides]

Charge trapping mechanism under dynamic stress and its effec...

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Annual International Symposium on reliability Physics

作者： G. Ghidini d. Brazzelli C. Clementi F. Pellizzer Non Volatile Memory Process Development Central R&D STMicroelectronics Agrate-Brianza Italy

The aim of this work was to investigate the effect of dynamic versus dC voltage stress applied to thin oxides. A longer lifetime was observed under pulsed stress at high electric fields. When increasing the frequency, we noticed an increment of lifetime and a different trapped charge location, regardless of the stress polarity. To detect the charge trapping evolution under pulsed stress, we used a new experimental procedure. Fast transitory phenomena detected using this technique are interpreted as charging and discharging of positive traps located in the anodic region. The consequent reduction of the effective positive charge allows us to explain the lifetime enhancement and the charge trapping evolution. We also compared the behaviour under pulsed stress of oxides grown in dry or steam environments. The lifetime increase is more relevant in dry oxides showing a correlation between the interface quality and the oxide reliability in dynamic mode.

关键词： Voltage Testing Pulse measurements dielectric substrates Electric breakdown Frequency Thermal stresses Charge carrier processes Monitoring Capacitors

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Inner cylinder Ta/sub 2/O/sub 5/ capacitor process for 1 Gb drAM and beyond

Inner cylinder Ta/sub 2/O/sub 5/ capacitor process for 1 Gb ...

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Symposium on VLSI Technology

作者： Seok Jun Won Yong Woo Hyung Kab Jin Nam Young dae Kim Ki Yeon Park Young Wook Park Sang In Lee Moon Young Lee Process Development Team Semiconductor R&D Center Samsung Electronics Company Limited Yongin si Gyeonggi South Korea

ISBN: (纸本)493081393X

Capacitor manufacturing technology for 0.13 /spl mu/m design rule 1 Gbit drAMs has been developed using an improved MIS (metal-insulator-semiconductor) tantalum oxide capacitor module process in a cylinder-shaped storage node with rugged-type inner surface (called inner cylinder). Capacitance of more than 26 fF/cell, leakage current of below 0.2 fA/cell at V/sub p/=1.0 V and breakdown lifetime of over 10 years were obtained as electrical properties, satisfying production level requirements.

关键词： Capacitors random access memory Annealing Testing Paper technology Curing Sorting dielectric measurements Breakdown voltage Very large scale integration

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