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Phase Change Memory: A review on Electrical Behavior and Use in Analog In-Memory-Computing (A-IMC) Applications

AdVANCEd ELECTrONIC MATErIALS 2024年第12期10卷

作者： Boniardi, Mattia Baldo, Matteo Allegra, Mario redaelli, Andrea STMicroelectronics Technol R&D I-20864 Agrate Brianza Italy

recent development and progress of Artificial Intelligence (AI) algorithms made clear that this topic is a paradigm shift with respect to the past. High throughput and ability to do complex tasks makes AI a great field of opportunity. This advancement is somehow limited by the physical implementation of the chips that are still bound to the historical von-Neumann Architecture with processing units and memory hardware spatially separated. The way data is bussed and processed needs disruptive innovation, rather than an evolutionary approach, too. In Analog In-Memory Computing (A-IMC) the typical properties of resistance-based memory technologies are used to both store and compute information. This allows for incredibly high parallelism and removes the problems related to the known von-Neumann bottleneck. In the present work, A-IMC networks based on resistive memories and on the Phase Change Memory (PCM) technology, in particular, are extensively discussed. After a first review of the general features of PCM devices, their application to A-IMC is described, aiming at a full description of the current technological scenario.

关键词： A-IMC ePCM GST Ge-GST MVM non-idealities compensation phase change memory

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Sustainable Technologies for responsible Products and a More Sustainable Future

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IEEE TrANSACTIONS ON SEMICONdUCTOr MANUFACTUrING 2024年第4期37卷 433-439页

作者： Nicoleau, S. Champseix, J. -l. Tagarian, d. Boeuf, F. Quinio, P. STMicroelectronics Dept Digital & Smart Power Frontend Technol R&D St F-38926 Crolles France STMicroelectronics Dept Digital & Smart Power Frontend Technol R&D St CH-1204 Geneva Switzerland STMicroelectronics Dept Digital & Smart Power Frontend Technol R&D St F-13106 Rousset France

The impact of human activity on the environment is well documented. While citizens and responsible leaders aim at a more sustainable future, it is our duty as industrial companies to examine our products portfolio from its life cycle perspective. A promising approach is to use sustainable manufacturing technologies, that minimize negative environmental impact, while boosting the product benefits towards decarbonization objectives. This paper enriches our earlier description (Nicoleau et al., 2023) of stmicroelectronics approach in developing sustainable technologies. It starts by examining the global context while putting in perspective the definition of responsible products. Then we will go through the different phases of the product lifecycle by illustrating the involved processes during technology development and product manufacturing. And we will complete our Life Cycle Assessment methodology by illustrating the efforts in striving to reduce our ecological footprint towards our ambition of carbon neutrality by 2027.

关键词： Sustainability responsible product responsible product sustainable technology sustainable technology carbon neutral carbon neutral

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Warpage modeling for semiconductor power module manufacturing flow improvement

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PrOCEEdINGS OF THE INSTITUTION OF MECHANICAL ENGINEErS PArT B-JOUrNAL OF ENGINEErING MANUFACTUrE 2024年第4期238卷 538-548页

作者： Calabretta, Michele Sitta, Alessandro rundo, Francesco Sequenzia, Gaetano STMicroelectronics Automot & Discrete Grp R&D Catania Italy Univ Catania Dipartimento Ingn Elettr Elettron & Informat DIEEI Catania Italy STMicroelectronics Automot & Discrete Grp R&D Stradale Primosole 50 I-95121 Catania Italy

The hybrid and battery electric vehicle market is heavily increasing the demand for semiconductor power modules. The manufacturing of such products is more complex than discrete devices. Some parameters, such as module deformation (warpage), play a major role. Power modules have to comply with customer Geometric dimensioning & Tolerancing (Gd & T) targets in order to avoid coolant leakage during operation and to guarantee mechanical compatibility with the driving board. Compliance with an appropriate flatness tolerance reduces rejects during manufacturing processes such as ultrasonic welding, and the consequent impact on reliability. due to these requirements, there is a need to implement dedicated countermeasures during manufacturing flows and to develop the proper methodologies to monitor flatness tolerances. Appropriate component selection at the design stage also limits flatness through the prediction of deformations during assembly flows using finite element model. This activity outlines the manufacturing flow for a direct cooled semiconductor power module and presents a method for product optimization in terms of flatness tolerance using a dedicated finite element model that calculates the warpage deformation induced by baseplate soldering and different ceramic substrate layouts. Furthermore, we describe experimental methodologies for measuring power module flatness and straightness across the manufacturing phases. dedicated experiments were conducted for methodological and design validation.

关键词： Power module flatness straightness tolerance finite element analysis

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Use of reinforcement Learning to improve GNSS satellites signal acquisition search strategy 4

Use of Reinforcement Learning to improve GNSS satellites sig...

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4th IEEE International Workshop on Metrology for Automotive (MetroAutomotive)

作者： Gogliettino, Giovani Pisoni, Fabio di Grazia, domenico STMicroelectronics ADG AAD GNSS R&D Arzano NA Italy STMicroelectronics ADG AAD GNSS R&D Cornaredo MI Italy

ISBN: (纸本)9798350384994;9798350384987

Satellite acquisition is a crucial procedure in GNSS receiver operation, which becomes particularly challenging when no assistance information is available - the so-called cold start conditions. In this paper, a machine learning approach will be introduced to improve the acquisition strategy. In detail, a reinforcement learning algorithm will be implemented to learn an optimal acquisition strategy.

关键词： GNSS GPS GALILEO GLONASS BEIdOU Positioning GNSS Acquisition Machine Learning reinforcement Learning

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Algorithm-Aware digital design for Analog-on-Top Chips: an ASK demodulator Comparative Study

Algorithm-Aware Digital Design for Analog-on-Top Chips: an A...

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IEEE Sensors Conference

作者： Tecce, Felice Abate, Matteo del Prete, Francesco Cirillo, Giovanni Amedeo Parrella, Claudio Castellano, Marco STMicroelectronics AMS R&D Arzano NA Italy STMicroelectronics AMS R&D Cornaredo MI Italy

ISBN: (纸本)9798350303872

design of application-specific digital Signal Processing elements is related to the implementation of an algorithm, initially implemented in software. The time-to-design can be extremely long, especially when design space exploration must be done and hardware description must be written from scratch. different tools are nowadays available to generate a register Transfer Level (rTL) circuit and corresponding testbenches from software, even with routines for design space exploration. These tools are based on High-Level Synthesis (HLS) and High-Language Hardware description (HLH) paradigms. This work compares the rTLs for an integrated digital Amplitude Shift Keying demodulator, employable either for the recognition of messages detected by transducers or in sensors networks. SystemVerilog, Catapult HLS from Siemens EdA and SpinalHdL were considered for canonical hardware description, HLS and HLH respectively. Synthesis results with three stmicroelectronics technologies prove that the rTLs automatically generated by SpinalHdL and Catapult provide area results comparable with those obtained with from-scratch design in SystemVerilog and can also achieve better performance in terms of dynamic power.

关键词： IP digital design High-Level Synthesis High-Language Hardware Hardware description Language Catapult SpinalHdL SystemVerilog Amplitude Shift Keying

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A Two-Stage CMOS Amplifier Performing High degree of Stability for All Capacitive Load

A Two-Stage CMOS Amplifier Performing High Degree of Stabili...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Bertolini, Alessandro Nicollini, Germano STMicroelectronics AMS R&D Design Dept Milan Italy

ISBN: (纸本)9798350330991;9798350331004

This paper presents the conception, design and realization of a fully-differential two-stage CMOS amplifier that is unconditionally stable for any value of the capacitive load. This is simply achieved by sending a scaled replica of the output stage current to the amplifier virtual ground such as to create a Left Half-Plane (LHP) zero in the loop-gain that either cancels or tracks the output pole in all process, voltage, and temperature (PVT) conditions. Consequently, from a stability point of view the amplifier behavior resembles that of a single-pole OTA. Starting from an existing two-stage gain-programmable amplifier, designed in a 0.18 mu m Bipolar-CMOS-dMOS (BCd) process, that was able to drive only 10pF without incurring into stability issues, a simple circuit has been added to extend the stability to any capacitive load value. Measurements, given with loads ranging from 0pF to 100nF, show high degree of stability in any load conditions. In the used 0.18 mu m BCd technology, silicon area and current consumption of the extra circuit are only 0.0004mm2 and 2 mu A, respectively, with a 5V power supply.

关键词： operational transconductance amplifiers Miller compensation large capacitive loads loop-gain

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A 13.92-ENOB 762ksps Bottom Sampling Capacitive SAr AdC for Medical Applications 39

A 13.92-ENOB 762ksps Bottom Sampling Capacitive SAR ADC for ...

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39th Conference on design of Circuits and Integrated Systems, dCIS 2024

作者： Ferlito, Umberto Ippolito, Calogero Marco Cassalini, Mirko Termini, danilo Bruno, Giuseppe STMicroelectronics APMS R&D Catania Italy

ISBN: (纸本)9798350364392

This paper presents the design of a bottom-sampling 762ksps 13.92-ENOB capacitive SAr Analog-To-digital Converter with embedded autocalibration tailored for medical applications. The IP has been developed using a HCMOS9A 130 nm technology from stmicroelectronics, but has been designed using the HCMOS9A GO2 option which only includes 500 nm minimum length MOS and require a 1.8 V supply. The proposed Converter achieves high resolution and speed, fulfilling the stringent demands of the PPG (photoplethysmogram) channel which requires at least 14-bit resolution and power-saving features such as the ability to turn OFF during inactive periods. The IP exhibits an average power dissipation of 4.86 mW during the conversion from 1.8 V supply and area employment of 0.806 mm 1.2. Conversion time is 1.3125 μs, comprising 0.3125 μs for the sampling and 16 clock cycles at 16MHz for the approximations. Simulation results have shown linearity and noise performances of a 14-bit converter, proving the goodness of the design. An auto-calibration technique improves the AdC's linearity up to 16 bits, ensuring that INL does not degrade the ENOB. © 2024 IEEE.

关键词： Medical applications

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A Wide Input Voltage range Buck Converter with Constant-Charge PFM Control 39

A Wide Input Voltage Range Buck Converter with Constant-Char...

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Applied Power Electronics Conference and Exposition (APEC)

作者： Melillo, Paolo Cremonesi, Lorenzo Leoncini, Mauro Gasparini, Alessandro Levantino, Salvatore Ghioni, Massimo Politecn Milan DEIB Milan Italy STMicroelectronics AMS R&D Milan Italy

ISBN: (纸本)9798350316643

Pulse frequency modulation (PFM) is widely used in buck converters to improve the efficiency at light loads. An adaptive on-time (AOT) control is usually adopted in wide input voltage range converters to mitigate the strong output voltage ripple variation. This paper presents a 6-V to 32-V input voltage, PFM buck converter with a novel AOT control that provides constant-charge current pulses over the whole input voltage range, resulting in an almost constant output voltage ripple. The prototype buck converter is fabricated in a 180-nm BCd process, and it provides an output voltage of 3.3-V and maximum load current of 100-mA with 92% peak efficiency. The proposed AOT control, which occupies only 0.04-mm(2), keeps the output voltage ripple almost constant around 40-mV, with a variation of only 7.5-mV over the whole input range.

关键词： Buck converter Pulse-frequency Modulation Adaptive on-time control voltage ripple.

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A 60 A Switched Tank Converter with Buck-Boost Sigma regulation for 48 V Bus down-Conversion 39

A 60 A Switched Tank Converter with Buck-Boost Sigma Regulat...

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Applied Power Electronics Conference and Exposition (APEC)

作者： Zaffin, Simone dago, Alessandro Leoncini, Mauro Gasparini, Alessandro Zambetti, Osvaldo Levantino, Salvatore Ghioni, Massimo Politecn Milan DEIB Milan Italy STMicroelectronics AMG R&D Milan Italy

ISBN: (纸本)9798350316643

In modern power distribution architectures, the conversion from the 48 V bus to the point of load (POL) voltage is performed in two steps. A switched tank converter (STC) first converts the bus voltage down to the 12 V level. Then, a POL converter provides the low supply voltage for CMOS circuitry. In the event of dC bus voltage fluctuations, however, the fixed conversion ratio of the STC forces the POL converter to operate with an input voltage that deviates from its nominal value. This paper introduces a sigma-converter that employs an additional inductor-based converter, coupled with the STC, to achieve output voltage regulation. Compared to prior art, the additional converter is connected to a different internal node of the STC, providing the peak efficiency at the nominal input voltage of 48 V, while guaranteeing high conversion efficiency over the whole 38 V to 60 V input voltage range. Moreover, a hybrid control strategy is suggested to guarantee voltage regulation when the input voltage hovers near its nominal value, with a control strategy to achieve seamless transitions upon the shift of the operating regime. A prototype converter has been implemented on a PCB to validate the proposed architecture, achieving a peak efficiency of 97.6 % at 30 A load current and 48 V input voltage, and a power density of 900 W/inch(3) at 60 A load current.

关键词： Electric power distribution

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A 10-MHz Three-Level Buck Converter with dual-Loop Time-Based Control and Flying Capacitor Voltage-Balance for Fast dVS 19

A 10-MHz Three-Level Buck Converter with Dual-Loop Time-Base...

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19th Conference on Ph.d research in Microelectronics and Electronics (PrIME)

作者： Magni, Gabriele Melillo, Paolo Bertolini, Alessandro Leoncini, Mauro Ghioni, Massimo Politecn Milan DEIB Milan Italy STMicroelectronics AMG R&D Milan Italy

ISBN: (纸本)9798350386301;9798350386318

High efficiency, small footprint and fast dynamic response are the key parameters of power management integrated circuits for portable applications. In this context, the three-level buck converter (TLBC) emerges as a practical solution, as it doubles the switching frequency and reduces the voltage swing at the switching node, compared to a conventional buck converter. As results, a small volume inductor can be employed, and high bandwidth can be achieved without compromising the converter's efficiency. However, precise regulation of the flying capacitor voltage at half the input supply is mandatory to ensure the reliable operation of the converter. This paper presents a dual-loop time-based control for a 10-MHz 2.8 similar to 3.6-V input and 0.6 similar to 1.2-V output TLBC. The proposed time-based controller merges the flying capacitor and the output voltage regulation in a single structure, thus minimizing the area occupation. The controller was designed in a 180-nm BCd technology. Simulations in SIMetrix/SIMPLIS demonstrates the efficacy and the robustness of the proposed control.

关键词： Three-Level Buck Converter Flying Capacitance Time-Based Control Voltage-balance

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