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39th Conference on design of Circuits and Integrated Systems, dCIS 2024

作者： Floridia, Andrea Grosso, Michelangelo STMicroelectronics S.r.l. APMS ACD Catania Italy STMicroelectronics S.r.l. APMS R&D Torino Italy

ISBN: (纸本)9798350364392

digital logic is typically tested by means of the scan chain methodology. Scan test procedures often need to be applied with different configurations (e.g., selectively activating certain clock domains or bypassing memory cores), which usually are dynamically set by means of functional or dedicated interfaces (e.g., IEEE 1149.1 JTAG). In addition, it may be useful to read some functional device data during the scan operation. This paper describes a novel approach for accessing in write or read mode some specific signals during the scan test procedure, employing the same protocol used for controlling scan chains and thus easing test generation and application. © 2024 IEEE.

关键词： Memory architecture

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Formal resilience Metric Characterization in Complex digital Systems 29

Formal Resilience Metric Characterization in Complex Digital...

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IEEE European Test Symposium (ETS)

作者： Zuccala, damian daveau, Jean-Marc roche, Philippe Morin-Allory, Kate Univ Grenoble Alpes Nanotech Dep Grenoble France STMicroelectronics R&D Dep Crolles France

ISBN: (纸本)9798350349320;9798350349337

As digital systems are continuously becoming more complex, new methods are required to ensure their resilience. research and industry are working together to develop automated formal methods, and, recently, great progress has been made to overcome this challenge. This work describes a general procedure to quantitatively determine, by Model Checking, the resilience level of a digital block whose flip-flops are perturbed by bit-flips. The flow relies on the formal proof, and provides a rich variety of results with much improved performance and accuracy (boost of similar to 300x and similar to 30x in the two test cases). The resilience metric is the number of distinct counterexamples provided by the formal engine, for each fault target. Failure traces are differentiated in two ways, showing on the test cases the great enhancement over simulation.

关键词： Safety resilience Fault Injection Model Checking

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Modelling the Elastic Energy of a Bifurcated Wafer: a Benchmark of the Analytical Solution vs. The ANSYS Finite Element Analysis

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COMPOSITE STrUCTUrES 2022年 281卷

作者： Vinciguerra, Vincenzo Malgioglio, Giuseppe Luigi Landi, Antonio STMicroelectronics ADG R&D Str Primosole 50 I-95121 Catania Italy

The phenomenon of bifurcation significantly impacts the warpage in wafers and consequently the yield and reliability of final systems in packages (SiPs). In this work, an analytical model of the dependence of the bifurcation energy of the substrate on the residual stress has been developed for a metalized wafer. The analytical model has been validated by exploiting Finite Element Analysis (FEA) methods. In the specific, ANSYS (r) simulation experiments have been designed to determine the substrate energy for the use-case of an 8 '' silicon 500 mu m thick wafer metalized with a 4.5 mu m aluminum layer, both in the spherical and bifurcation regime. In the simulations, the bifurcation case has been induced in the wafer by applying a pair of weak forces acting as perturbations along two perpendicular diameters. The applied forces and the energy of the substrate has been assessed within a theoretical framework. The resulting principal curvatures of the wafer have been analyzed according to the bifurcation diagram reported by the theory. Moreover, it is proven that the bifurcation energy is systematically lower with respect to the spherical case as the residual stress increases and has a second order power law predicted by the analytical model. The findings of the paper can be extended to other semiconductor substrates such as silicon carbide (SiC).

关键词： Bifurcation Wafer Warpage Curvature Finite Element Analysis (FEA) Simulations

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Time-Based Buck Converter with Variable Frequency dCM and ON-Time Correction for Seamless Transitions 18

Time-Based Buck Converter with Variable Frequency DCM and ON...

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18th International Conference on Ph.d research in Microelectronics and Electronics (PrIME)

作者： Melillo, Paolo Zaffin, Simone Gasparini, Alessandro Levantino, Salvatore Ghioni, Massimo Politecn Milan DEIB Milan Italy STMicroelectronics R&D Milan Italy

ISBN: (纸本)9798350303209

A time-based compensator represents an effective solution to overcome the limitations of the traditional voltage mode controllers, as it allows to reduce both the die area occupation and the quiescent power consumption without compromising the control loop performances. Buck converters driven by high switching frequencies suffer from relatively low efficiency in medium/light load conditions, given the large power losses associated to the switching activity. Usually, to overcome this limitation the converter is operated in pulse frequency modulation (PFM), which makes it necessary to design an additional control loop and adds a dC offset to the output voltage as well. This paper proposes a variable switching frequency time-based control, able to operate the converter both in continuous and discontinuous current mode to guarantee high efficiency for a wide load current range. In addition, seamless frequency transition are obtained with a dedicated on-time correction circuit, which keeps the average inductor current constant upon variations of the operating regime. The proposed method boosts the efficiency in medium-light load conditions, ensuring an overall efficiency above 85% over a wide load current range. The effectiveness of this technique is supported by theoretical analysis and simulation results.

关键词： on-time correction variable frequency buck converter time-based control dCM operation

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Analytical Approach for Preliminary deformation Investigation 40

Analytical Approach for Preliminary Deformation Investigatio...

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40th IEEE International Electronics Manufacturing Technology, IEMT 2024

作者： duca, roseanne Backend Manufacturing & Technology R&d STMicroelectronics Ltd Industry Road Kirkop Malta

ISBN: (纸本)9798350388824

The objective of this study is to compare the results from experiment and modeling on simplified models with those from analytical solution. The target is to understand if simple analytical models or tools can be used for fast indication and preliminary evaluation of material behavior. Simple samples and respective models will be built and evaluated for warpage at temperatures of interest, namely room temperature and reflow temperature. Following this an analytical approach using Timoshenko beam formula will be evaluated and results compared with the experimental and modeling results. Finally, it will be decided if and how a simplified tool can be developed for fast and preliminary results for material comparison basis as a means of eliminating material that will not reach the desired performance prior to building more elaborate models or samples. The analysis focuses on bi-material structures for the time being and hence is more suited as a rough estimate for frame based packages, though an example for a Ball Grid Array (BGA) package is also presented. The assumptions and limitations of this methodology will be outlined. Keywords - packaging, thermo-mechanical modeling, Timoshenko equation, warpage, finite element analysis (FEA), package design, analytics (key words) © 2024 IEEE.

关键词： Ball grid arrays

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Integrated GaN digital soft start-up for switching power converters 18

Integrated GaN digital soft start-up for switching power con...

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18th International Conference on Ph.d research in Microelectronics and Electronics (PrIME)

作者： Samperi, Katia Spina, Nunzio Pennisi, Salvatore Palmisano, Giuseppe Univ Catania DIEEI Catania Italy STMicroelectronics R&D ADG Catania Italy

ISBN: (纸本)9798350303209

This paper presents an integrated soft start-up circuit implemented in a 0.5-mu m GaN on Si technology suitable for on-chip integration in power applications. The proposed approach avoids the use of large on-chip or external capacitors to overcome the problem of voltage overshoot and inrush current at start up in switching power converters. It could be also adapted to the specific application by choosing the number of Flip Flops, or, for large start-up periods, using a counter, and setting the desired start-up signal duty cycle. Moreover, an optimized Flip Flop circuit topology has been proposed to reduce area occupation. The circuit working principle and the design challenges in GaN technology are discussed together with simulations. The circuit has been designed by considering worst-case conditions. A test buffer has been also included to drive the high external load capacitance of the readout device. Measured waveforms are reported that demonstrate the effective circuit operation and suitability for all-GaN integration.

关键词： Soft-Start Inrush Current Voltage Overshoot GaN ICs GaN power converter

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Study of Solder Ball Hardness on Wafer Level Chip Size Packages 40

Study of Solder Ball Hardness on Wafer Level Chip Size Packa...

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40th IEEE International Electronics Manufacturing Technology, IEMT 2024

作者： Mon, Aye Aye Yap, daniel STMicroelectronics Pte Ltd Back End Manufacturing & Technology R&d Toa Payoh Singapore

ISBN: (纸本)9798350388824

There are some challenges in electronic industries to achieve robustness in Thermal Cycling performance on board for big Wafer Level Chip Size Packages (WLCSP), though usually no concern or robust in drop Test reliability, partly WLCSP is typically less ball counts and much smaller package size compared to Ball-Grid-Array (BGA). It is essential to balance the solder joint hardness for the overall robustness in the field application where the WLCSP could be subjected various loading conditions like Thermal Cycling Test on Board (TCoB), Bend, drop etc. In this paper, solder joint hardness was studied for different solder alloy Sn-Ag-Cu of WLCSPs on PCB board before and after thermal cycling test (e.g. 1000 cycles) to improve the TC on Board performance. Berkovich micro indentation technique was used and optimized for providing precise and consistent measurements of indentation hardness. The experimental results showed that hardness of solder alloy induced by Ag or different % in Bi, solder paste, faster cooling after reflowing, softening during annealing and deterioration during TC, which may eventually affect the TCoB performance. Hardness could be a good, simple, and cost-effective indicator for solder joint reliability. It can be used for alloy selection, reflow profile optimization, and investigating aging impact etc. © 2024 IEEE.

关键词： Ball grid arrays

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Simulation informed method to compare experimental and numerical results in plastic packages 26

Simulation informed method to compare experimental and numer...

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26th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2025

作者： Carasi, Beatrice Viganò, Giovanni Spini, daniela Napolitano, Teresa Cecchetto, Luca Smart Power TR&D - CPI STMicroelectronics Milan Italy Smart Power TR&D - EWS STMicroelectronics Milan Italy BEM&T R&D STMicroelectronics Agrate Brianza Italy AMS R&D STMicroelectronics Milan Italy

ISBN: (纸本)9798350393002

This paper describes the first steps in the realization of a quantitative plastic package numerical model to evaluate circuit performance changes due to stress in silicon. Leveraging the piezoresistive effect and simple resistors electrical measurements, combined with some considerations spawned by symmetry and simulation output, we can compare directly the measured (function of the electrical output) and the computed stress field. Warpage is also considered to correlate the numerical model and the experiments. It will be shown that a simple linear elastic model is unable to predict the stress field and the warpage with enough accuracy and there is a need to develop a more predictive simulation model. © 2025 IEEE.

关键词： integrated circuits mechanical simulation piezoresistive effect plastic package

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Models of Bifurcation and Gravity Induced deflection in Wide Band Gap 4H-SiC Semiconductor Wafers 24

Models of Bifurcation and Gravity Induced Deflection in Wide...

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24th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)

作者： Vinciguerra, Vincenzo Malgioglio, Giuseppe Luigi Landi, Antonio renna, Marco STMicroelectronics ADG R&D Stradale Primosole 50 I-95121 Catania Italy

ISBN: (纸本)9798350345971

Handling and warpage control of larger and thinner semiconductor wafers can be critical within the large-scale semiconductor manufacturing process. With the development of 8" wide band gap substrates pilot lines, e.g. based on silicon carbide, similar issues may emerge. In particular, the lack of containment of the warpage at early stages in the manufacturing process may evolve into the phenomenon of wafer bifurcation, consisting in an uncontrolled asymmetric warpage. This can occur also for the case of 8" 4H-SiC substrates. In this work, the investigation of the phenomenon of wafer bifurcation has been extended to the case of a 4HSiC ( 0001) 8" wafer, metallized with a thin layer of aluminum. For the SiC substrates, we investigated both the spherical and bifurcation regime, through finite element analysis (FEA) methods, by using ANSYS (r) tools. In particular, the bifurcation has been induced in the wafer by applying a pair of weak forces as perturbations along two perpendicular directions acting normally with respect to the wafer surface. Moreover, the deflection induced by the action of Earth's gravity on bare SiC 8" thinned wafers has also been considered. Indeed, gravity induced deflection (GId) is a factor that can influence the handling, move and load of wafers in an 8" production line. In the paper, the GId of a 8" SiC plain wafer fixed at two points is compared with the case of the same wafer supported at four points. In this work a preliminary evaluation of the GId and a solution to reduce it is proposed by means of ANSYS simulations tools.

关键词： Bifurcation Curvature Finite Element Analysis (FEA) Gravity Induced deflection Simulations Wafer Warpage

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A Triple-Band GNSS receiver for High Accuracy Automotive Applications 2

A Triple-Band GNSS Receiver for High Accuracy Automotive App...

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2nd IEEE International Workshop on Metrology for Automotive (IEEE MetroAutomotive)

作者： di Grazia, domenico Pisoni, Fabio Gogliettino, Giovanni Ardiero, Simone Avellone, Giuseppe STMicroelectronics ADG AAD GNSS R&D Arzano NA Italy STMicroelectronics ADG AAD GNSS R&D Milan Italy STMicroelectronics ADG R&D Safety & Design Qual Catania Italy

ISBN: (数字)9781665466899

ISBN: (纸本)9781665466899

Among on-board sensors, the Global Navigation Satellite System (GNSS) receiver plays a key role because of its unique capability of absolute and precise localization. Autonomous vehicles guidance and assistance, resilient timing and an increased demand for higher safety levels are motivating a rapid evolution toward multi-band GNSS receivers in the automotive (and industrial) segments. Triple-band GNSS has gained interest in the past years and found application in professional receivers and reference stations, mostly because of faster carrier-phase ambiguity resolution, stronger integrity constraints over linear combinations and higher signal availability for real-Time Kinematic (rTK) algorithms. The deployment of new services for high-accuracy positioning, like Galileo HAS, Beidou PPP-B2b and Quasi Zenith Satellite System (QZSS) CLAS is also taking benefit from the availability of multiple bands. In this latest applicative scenario, the third frequency plays a different role, acting as an additional downstream channel for the GNSS correction data. Signal modernization is definitely another strong enabler for the adoption of triple-band. With specific reference to system design and signal processing aspects, this article discloses a new compact GNSS chipset for automotive, capable to generate coherent triple band observables and correction data streams, including a demodulator for QZSS Code Shift Keying (CSK). The frequency plans, the supported mix of legacy and modernized signals and relevant Key Performance Indicators (KPI) are discussed for selected configurations, typically encountered in automotive precise-positioning and timing.

关键词： GNSS satellite navigation automotive precise positioning corrections CSK multi-band modernized signals high accuracy

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