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High Power density 4:1 resonant Switched-Capacitor dC-dC Converter for PoL Applications 38

High Power Density 4:1 Resonant Switched-Capacitor DC-DC Con...

引用

IEEE Applied Power Electronics Conference and Exposition (APEC)

作者： dago, Alessandro Leoncini, Mauro Brunero, Alberto Gasparini, Alessandro Zambetti, Osvaldo Levantino, Salvatore Ghioni, Massimo Politecn Milan DEIB Milan Italy STMicroelectronics AMG R&D Milan Italy

ISBN: (纸本)9781665475396

In recent years, resonant switched-capacitors converters (reSCC) proved to be a valid alternative to traditional buck converters, thanks to their key features such as very high power density, high efficiency, and capability of adjusting the output voltage through quasi-resonant operation. However, since the components count increases with the conversion ratio, these advantages are usually limited to reSCC topologies providing 2:1 nominal down-conversion. This paper presents a novel dC/dC reSCC topology that performs a nominal 12 to 3 V (4:1) down-conversion. Thanks to the minimum number of components and the use of parasitic PCB inductors, a peak power density of 0.53 W/mm(2) is reached at 5 A current load, while the peak efficiency is 94.4 %. A novel control system for 3-phase quasi-resonant operation is then introduced, enabling fine output voltage regulation below the 3 V nominal output voltage value.

关键词： Topology

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A Compact Wide-Input-range Time-domain Buck Converter with Fast Transient response for Industrial Applications 49

A Compact Wide-Input-Range Time-Domain Buck Converter with F...

引用

IEEE 49th European Solid-State Circuits Conference (ESSCIrC)

作者： Melillo, Paolo Leoncini, Mauro Zaffin, Simone Brunero, Alberto Gasparini, Alessandro Levantino, Salvatore Ghioni, Massimo Politecn Milan DEIB Milan Italy STMicroelectronics AMG R&D Milan Italy

ISBN: (纸本)9798350304206

Time-domain control in dC-dC converters represents an effective strategy to reduce the controller area occupation without introducing the quantization error typical of digital approaches. Because of the absence of the PWM ramp generator, however, the implementation of line feed-forward compensation in a time-domain controller is not straightforward. This paper introduces a time-domain-controlled buck converter with a line feed-forward and an adaptive loop gain compensation. A 1.4-A prototype converter with 6-to-24-V input voltage range and 3.3-V output, is fabricated in a 180-nm BCd process. Experimental results show a 3x reduction in the line transient response and a control loop bandwidth with limited dependence on input voltage variations. The die area is 1.78 mm(2), while the time-domain controller occupies only 0.28 mm(2).

关键词： dC-dC converters time-domain control feed-forward compensation control

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High Performance MEMS IMU with ThELMA-double Technology 9

High Performance MEMS IMU with ThELMA-Double Technology

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9th IEEE International Symposium on Inertial Sensors and Systems (IEEE INErTIAL)

作者： Gattere, G. rizzini, F. Guerinoni, L. Falorni, L. Valzasina, C. Vercesi, F. Corso, L. Allegato, G. STMicroelectronics AMS R&D Milan Italy

ISBN: (纸本)9781665402828

This paper presents the design, architecture, and characterization of stmicroelectronics first prototype 6-axis Inertial Measurement Unit (IMU) manufactured with a novel micromachining technology. The platform novelty consists in the fabrication of structural and electrical elements using multiple independent thick epitaxial polysilicon layers. The performance of the device with respect to standard technology is deeply analyzed through the state-of-art characterization steps of stmicroelectronics IMU production. The improvements in terms of electrical figures, parametric stability and mechanical robustness are presented.

关键词： MEMS IMU ThELMA-double Performance Stability Mechanical robustness

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dielectric Breakdown of in-Package Epoxy Mold Compound under Wet and dry Conditions: Frequency and Temperature dependence 26

Dielectric Breakdown of in-Package Epoxy Mold Compound under...

引用

26th Electronics Packaging Technology Conference, EPTC 2024

作者： Balestra, Luigi riaz, Muhammad Tanveer Giuliano, Federico Cavallini, Andrea reggiani, Susanna Oldani, Luca Guarnera, Simone Salvatore rossetti, Mattia depetro, riccardo ARCES & DEI University of Bologna Bologna Italy Smart Power R&D STMicroelectronics Cornaredo Italy

ISBN: (纸本)9798331522001

Epoxy-based molding compounds (EMCs) are highly valued materials in the electronics industry due to their strong resistance to a variety of mechanical, electrical, and environmental stresses. In literature, EMCs were characterized by using thick bulk samples providing interesting indications on their electrical reliability when employed in high humidity, voltage and temperature conditions. However, in-package performance and reliability with thin EMC structures is lacking. In this work, an interdigitated capacitor embedded into a 24-pin Single-Small-Outline (SSO) package is used as a reference test structure. Samples have undergone rigorous realization and preliminary characterization procedures. The features of EMC layers as thin as 15.7μm have been measured up to the dielectric breakdown by applying dC and AC ramp voltages under different humidity, frequency and temperature. results show that the breakdown strength is higher under dC voltage stress than AC ones. Moreover, the relationship between the breakdown strength and frequency in dry conditions has a statistically significant dependence: the greater the frequency, the lower the breakdown strength. On the contrary, almost no dependency between breakdown strength and temperature has been observed under both wet and dry conditions. The presence of space charge is expected to play a key role in each dependence. Thus, a preliminary TCAd model is proposed to effectively explain the role of space charge formation at different ramp rates. © 2024 IEEE.

关键词： Electronics industry

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Finite Element Analysis of the upscaling of Warpage and Bifurcation Hysteresis Loops: from Cu/Si die to Large Wafers

Finite Element Analysis of the upscaling of Warpage and Bifu...

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2024 International Exhibition and Conference for Power Electronics, Intelligent Motion, renewable Energy and Energy Management, PCIM Europe 2024

作者： Vinciguerra, Vincenzo Malgioglio, Giuseppe Luigi renna, Marco Power & Discrete Technologies R&D Department STMicroelectronics Stradale Primosole 50 Catania95121 Italy

ISBN: (纸本)9783800762620

Large semiconductor wafers with thick electrochemical deposited copper (Cu_ECd) layers suffer from severe warpage during the final thinning process. This can lead to an asymmetric warpage or bifurcation of the wafer. Finite element analysis software can predict the phenomenon of warpage and bifurcation, but an accurate prediction requires considering the plastic behavior of the metal layer. The study investigated the extension of a finite element analysis multilinear kinematic hardening model of plastic Cu_ECd from a die level to the wafer level to predict the warpage hysteresis loop and deduce the phenomenon of bifurcation during the thinning process of a 200 mm standard wafer. © VdE VErLAG GMBH · Berlin · Offenbach.

关键词： Hysteresis loops

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EFFECT OF FrEQUENCY ON rELIABILITY OF High-K MIM CAPACITOrS 61

EFFECT OF FREQUENCY ON RELIABILITY OF High-K MIM CAPACITORS

引用

61st IEEE International reliability Physics Symposium (IrPS)

作者： Federspiel, X. Griffon, A. Barlas, M. Lamontagne, P. STMicroelectronics Technol R&D 850 Rue Jean Monnet F-38926 Crolles France

ISBN: (纸本)9781665456722

dielectric relaxation phenomena in High-K capacitors have been reported to induce transitory effects. We present here a TddB analysis including dC and pulsed dC stress applied on HK capacitors. We evidence a significant effect of frequency on TddB. Using a model based on dielectric polarization dynamics, we found a good agreement with TddB evolution with frequency but also a consistent behavior in terms of voltage acceleration factor as well as activation energy.

关键词： High-K capacitor reliability frequency polarization TddB

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Intelligent Electrical Assessment of Silicon and Silicon Carbide Wafers for Power Applications in Automotive Field 4

Intelligent Electrical Assessment of Silicon and Silicon Car...

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4th IEEE International Workshop on Metrology for Automotive (MetroAutomotive)

作者： rundo, Francesco Calabretta, Michele rundo, Michael S. Castagnolo, Giulia Pino, Carmelo Battiato, Sebastiano Messina, Angelo A. STMicroelectronics P&D R&D QMT Catania Italy Univ Catania DIEEI PeRCeiVe Lab Catania Italy Univ Catania DMI IPLAB Catania Italy STMicroelectronics IPA Grp Catania Italy

ISBN: (纸本)9798350384994;9798350384987

detecting and identifying production defects in the semiconductor industry are crucial for maintaining quality control during manufacturing. The use of new materials, such as Silicon and Silicon Carbide, highlights the need for a reliable wafer defect detection system. The Electrical Wafer Sorting (EWS) stage, which involves an electrical analysis of defect maps, is effective in spotting anomalies and defect patterns on wafers. This phase is time-consuming but enables semiconductor companies to improve and optimize their manufacturing processes, including the integration of advanced deep learning techniques. The proposed pipeline aims to meet the demand for a fully automated system to identify manufacturing defects in wafers, utilizing intelligent analysis of EWS wafer maps in combination with a deep Convolutional Neural Network and an unsupervised subsystem. The stringent level of intelligent control at the EWS stage is necessary because the devices produced from the analyzed wafers are mainly power devices used in the power and inverter systems of the latest generation of conventional and electric cars. Experimental results have confirmed the effectiveness of this approach.

关键词： Pattern recognition deep learning Silicon Silicon Carbide defect Analysis

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Machine Learning-based feasibility estimation of digital blocks in BCd technology

Machine Learning-based feasibility estimation of digital blo...

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2024 IEEE International Conference on design, Test and Technology of Integrated Systems, dTTIS 2024

作者： daghero, Francesco Faraone, Gabriele Grosso, Michelangelo Pagliari, daniele Jahier di Carolo, Nicola Franchino, Giovanna Antonella Licastro, dario Serianni, Eugenio Politecnico di Torino Department of Control and Computer Engineering Turin10129 Italy STMicroelectronics Power & Discrete MEMS Sensor R&D Group 20864 Italy STMicroelectronics Power & Discrete MEMS Sensor R&D Group Turin10129 Italy

ISBN: (纸本)9798350363128

Analog-on-Top Mixed Signal (AMS) Integrated Circuit (IC) design is a time-consuming process predominantly carried out by hand. Within this flow, usually, some area is reserved by the top-level integrator for the placement of digital blocks. Specific features of the area, such as size and shape, have a relevant impact on the possibility of implementing the digital logic with the required functionality. We present a Machine Learning (ML)-based evaluation methodology for predicting the feasibility of digital implementation using a set of high-level features. This approach aims to avoid time-consuming Place-and-route trials, enabling rapid feedback between digital and Analog Back-End designers during top-level placement. © 2024 IEEE.

关键词： Adversarial machine learning

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Long GNSS Secondary Codes Acquisition by Characteristic Length Method 3

Long GNSS Secondary Codes Acquisition by Characteristic Leng...

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3rd IEEE International Workshop on Metrology for Automotive (IEEE MetroAutomotive)

作者： di Grazia, domenico Pisoni, Fabio Crasta, Salvatore Napolitano, Antonio darsena, donatella Ardiero, Simone STMicroelectronics ADG AAD GNSS R&D Arzano NA Italy STMicroelectronics ADG AAD GNSS R&D Cornaredo MI Italy Univ Napoli Parthenope Naples Italy Univ Napoli Federico II Naples Italy

ISBN: (纸本)9798350321876

Global Navigation Satellite System (GNSS) receiver evolution moves through the paths of interoperability among different satellite systems and the support of modern composite signals. To improve the receiver accuracy, the tracking sensitivity, and the resilience versus jamming, modern signals have introduced dual (pilot plus data) components. Pilot signals design on L1 carrier for GPS, Beidou (phase 3), and Quasi-Zenith Satellite System (QZSS) are implemented by tiered codes, with a very long Secondary Code (SC), which can be difficult to acquire. This article will analyze and validate an efficient algorithm for secondary code phase estimation, with the objectives to minimize the total dwell time and to limit the processing complexity. details will be provided about the performance tradeoff versus other classic algorithms, based on the exhaustive construction of power histograms, for all the SC phases. A method for fast reacquisition of the SC phase, based on time propagation, will be also illustrated to extend the practical usability of the estimator under difficult conditions, characterized by obscurations and signal impairments, typical of automotive scenarios.

关键词： GNSS Tiered Signals Secondary Codes acquisition Characterist length Concept Beidou B1C GPS-QZSS L1C STA8135GA

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Power Board design for Parallel SiC MOSFET Characterization

Power Board Design for Parallel SiC MOSFET Characterization

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2024 Energy Conversion Congress and Expo Europe, ECCE Europe 2024

作者： Spitaleri, Maria Giorgia Scarcella, Giuseppe Scelba, Giacomo Latella, Marco Cocuzza, Agostino Bottaro, Enrico Alfredo Vinci, Giovanni University of Catania Dieei Catania Italy STMicroelectronics Power Tran. Sub Group Catania Italy STMicroelectronics Ams R&d Catania Italy

ISBN: (纸本)9798350364446

The primary objective of this paper is to present the design of a power board specifically developed to investigate the impact of parameters and layout mismatches of paralleled SiC dies used in power modules. The layout of the half-bridge power board has been realized minimizing asymmetries among the parallel branches and including specific additional paths to modulate parasitic elements and decoupling resistances. In this way, current imbalance and differential-mode inter-chip oscillations can be investigated. © 2024 IEEE.

关键词： Power MOSFET

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