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A 512×512 SPAd Laser Speckle Autocorrelation Imager in Stacked 65/40nm CMOS

A 512×512 SPAD Laser Speckle Autocorrelation Imager in Stac...

引用

2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024

作者： della rocca, Francescopaolo Mattioli Sie, Edbert J. Erdogan, Ahmet T. Fisher, Lars Matheson, Andrew B. Finlayson, Neil Gorman, Alistair Gyongy, Istvan Mai, Hanning Lachaud, Thierry Forsyth, russell Marsili, Francesco Henderson, robert K. School of Engineering The University of Edinburgh Edinburgh United Kingdom Reality Labs Research Meta Platforms Inc. Menlo Park United States STMicroelectronics R&d United States

ISBN: (纸本)9798350361469

We present a single-photon avalanche diode (SPAd) autocorrelation imager implemented in 65/40nm 3d-stacked CMOS for laser speckle blood flow monitoring. The shared per-pixel SrAM architecture provides a compact 41.68 μm pitch 128×128 resolution parallel autocorrelation function operating at 0.5T Op/s and a lag-time of 1 μs. SNr gains due to high BSI SP Ad NIr sensitivity and on-chip averaging extends source-detector separation to 40 mm indicative of the sensitivity required to discriminate extracerebral artifacts from deep-tissue blood flow in future wearable neuromonitoring systems. © 2024 IEEE.

关键词： autocorrelation CMOS dCS SPAd

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Finite Element Analysis of Warpage Hysteresis Loop Evolution and Bifurcation in thinned 4H-SiC Cu_ECd metalized Wafers 26

Finite Element Analysis of Warpage Hysteresis Loop Evolution...

引用

26th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2025

作者： Vinciguerra, Vincenzo Malgioglio, Giuseppe Luigi renna, Marco Quality Manufacturing and Technology (QMT) Power & Discrete Technologies R&D Department STMicroelectronics Catania Stradale Primosole 50 Catania 95121 Italy

ISBN: (纸本)9798350393002

The thinning of large wafers often leads to increased warpage due to residual stress, adversely affecting wafer processability and chip-to-package interaction (CPI). Mitigating wafer warpage, particularly preventing its progression to critical phenomena such as bifurcation or buckling, is crucial in the manufacturing also of large widebandgap semiconductor wafers of 4H-SiC. This study advances the investigation of the warpage hysteresis loop (WHL) evolution by examining the progression towards bifurcation in highly stressed layers, specifically focusing on electrochemically deposited copper (Cu_ECd) on thinned 4H-SiC (0001) wafers. Exploiting ANSYS finite element analysis (FEA), the research considers the asymmetries of bifurcation in Si (001) and SiC (0001) wafers during the thinning process. The study provides a comparative analysis of the WHL evolution in Si (001) wafers versus 4H-SiC (0001) wafers, offering insights into the distinct behaviors of these materials under stress. © 2025 IEEE.

关键词： 4H-SiC Bifurcation Buckling Copper ECd Finite Element Analysis Warpage Hysteresis Loop

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Out of Plane double differential Quadrature Compensation Electrodes with ThELMA-double Technology

Out of Plane Double Differential Quadrature Compensation Ele...

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2023 IEEE International Symposium on Inertial Sensors and Systems (INErTIAL)

作者： P. Fedeli L. Falorni G. J. Yallico Sanchez M. riani G. Gattere STMicroelectronics AMS R&D Milan Italy

In this paper, a new architecture of double differential quadrature compensation electrodes to enable high performance gyroscope is presented. Their fabrication is allowed by a novel micromachining technology, known as ThELMA-double process [1], which is an evolution of standard stmicroelectronics ThELMA technology. Analytical and numerical models have been adopted during the design steps to estimate the advantages of this innovative structure as compared to standard solution. The focus is on increasing the quadrature compensation capability and improving the scale factor stability. Preliminary experimental characterization proves the validity of the simulation models and the effectiveness of the proposed architecture.

关键词： Electrodes Micromechanical devices Simulation Prototypes Micromachining Stability analysis Numerical models

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Use of reinforcement Learning to Improve GNSS Satellites Signal Acquisition Search Strategy

Use of Reinforcement Learning to Improve GNSS Satellites Sig...

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Metrology for Automotive (MetroAutomotive), IEEE International Workshop on

作者： Giovani Gogliettino Fabio Pisoni domenico di Grazia ADG – AAD GNSS R&D STMicroelectronics Arzano NA Italy

ISBN: (数字)9798350384987

ISBN: (纸本)9798350384994

Satellite acquisition is a crucial procedure in GNSS receiver operation, which becomes particularly challenging when no assistance information is available - the so-called cold start conditions. In this paper, a machine learning approach will be introduced to improve the acquisition strategy. In detail, a reinforcement learning algorithm will be implemented to learn an optimal acquisition strategy.

关键词： Knowledge engineering Global navigation satellite system Satellites Q-learning Machine learning algorithms Stochastic processes receivers

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Effect of Frequency on reliability Of High-K MIM Capacitors

Effect of Frequency on Reliability Of High-K MIM Capacitors

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Annual International Symposium on reliability Physics

作者： X. Federspiel A. Griffon M. Barlas P. Lamontagne Technology R&D STMicroelectronics Crolles France

dielectric relaxation phenomena in High-K capacitors have been reported to induce transitory effects. We present here a TddB analysis including dC and pulsed dC stress applied on HK capacitors. We evidence a significant effect of frequency on TddB. Using a model based on dielectric polarization dynamics, we found a good agreement with TddB evolution with frequency but also a consistent behavior in terms of voltage acceleration factor as well as activation energy.

关键词： Polarization Capacitors Voltage MIM capacitors dielectrics reliability High-k dielectric materials

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Analytical Approach for Preliminary deformation Investigation

Analytical Approach for Preliminary Deformation Investigatio...

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IEEE/CHMT(CPMT) International Electronics Manufacturing Technology Symposium

作者： roseanne duca STMicroelectronics Ltd Backend Manufacturing & Technology R&D Kirkop Malta

ISBN: (数字)9798350388824

ISBN: (纸本)9798350388831

The objective of this study is to compare the results from experiment and modeling on simplified models with those from analytical solution. The target is to understand if simple analytical models or tools can be used for fast indication and preliminary evaluation of material behavior. Simple samples and respective models will be built and evaluated for warpage at temperatures of interest, namely room temperature and reflow temperature. Following this an analytical approach using Timoshenko beam formula will be evaluated and results compared with the experimental and modeling results. Finally, it will be decided if and how a simplified tool can be developed for fast and preliminary results for material comparison basis as a means of eliminating material that will not reach the desired performance prior to building more elaborate models or samples. The analysis focuses on bi-material structures for the time being and hence is more suited as a rough estimate for frame based packages, though an example for a Ball Grid Array (BGA) package is also presented. The assumptions and limitations of this methodology will be outlined. Keywords—packaging, thermo-mechanical modeling, Timoshenko equation, warpage, finite element analysis (FEA), package design, analytics (key words)

关键词： Temperature measurement Semiconductor device modeling Analytical models Temperature distribution Semiconductor device measurement deformation Computational modeling Thermomechanical processes Mathematical models Silicon

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Switching control to enhance performance in smart protections

Switching control to enhance performance in smart protection...

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IEEE International Symposium on Industrial Electronics (ISIE)

作者： Manuela La rosa Giovanni Sicurella Salvatore d’Angelo davide Patti donata Nicolosi Technology R&D Smart Power STMicroelectronics Catania Italy AMS -General Purpose Analog STMicroelectronics Catania Italy AMS R&D STMicroelectronics Catania Italy

Smart protections, such as E-Fuses (Electronic Fuses), ensure a higher level of quality and reliability in enterprise data storage, industrial and telecom/networking applications. The proposed architecture allows building novel protection devices that operate in case of overvoltage and current limitation conditions. This new approach is based on a switching control performed by four comparators that are smaller in area than the Operational Amplifiers, traditionally used to regulate the Output Voltage and Current in case of fault. A new device (Switching E-Fuse) is designed with considerable enhancement of protection speed. It allows a considerable reduction of silicon area, up to 50%, compared to linear approach and thus an higher profitability than known solutions. Moreover, control speed enhancement strongly reduces stress conditions, thus increasing target application lifetime and reliability. A monolithic silicon demonstrator has been realized using a 180 nm Smart Power Technology.

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Industrialization of a New Adhesion Promoter Process for Leadframe 40

Industrialization of a New Adhesion Promoter Process for Lea...

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40th IEEE International Electronics Manufacturing Technology, IEMT 2024

作者： Crema, Paolo Neoh, din Ghee Villa, riccardo Lee, Boon Seong Ohde, Christian STMicroelectronics Bem&t R&d MB Agrate Brianza Italy Singapore Singapore Atotech Germany GmbH & Co. Kg Bu Sf /SC/ Fec Berlin Germany

ISBN: (纸本)9798350388824

Substrate-based microelectronics have become common these days, but leadframe-based packages are still widely used in the semiconductor industry. Increased reliability requirements have led to extensive adoptions of "adhesion promoter"technologies on leadframes, to enhance the adhesion between leadframe metal surfaces and chip encapsulation materials, such as epoxy molding compounds (EMC). With the introduction of the most stringent requirement of the automotive electronics industry, many plastic packages, such as QFP, tend to show their weaknesses in delamination even during early *** degree of EMC delamination is usually found near the lead bonding areas on the leadframe, which are typically Ag-plated and Ag surfaces have very poor adhesion to EMC. If gold wires were used as the interconnects between the die and the leadframe, the gold wires may still be intact after package preconditioning due to their high ductility properties. driven by cost initiatives, Cu wires have been introduced to replace gold wires. Cu wire introduction brings several workability challenges that require specific process optimizations on each leadframe finish [1]. Under such circumstances, severe problems of stitch bond cracks could occur and lead to serious package reliability issues due to the lower elongation of Cu *** adhesion can be improved acting on leadframe finishing: different plating stacks or roughening techniques can achieve a better adhesion, however those solutions will imply a significant leadframe cost increase, as well as the workability during IC assembly processes. In this paper, we will share the major challenges faced during the industrialization of a new adhesion promoter process, which is applicable to Ag surfaces and do not require surface etching or roughening;this study will also address the ultimate adhesion performance at high temperature of the new adhesion promoter and other key benefits of this noble process. © 2024 IEEE.

关键词： reliability

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Experimental Study of Force Induced by Probe Length Influence on Electrical Contact resistance of Pillar Bump-Flat Vertical Probe Interaction during Wafer Electrical Test

Experimental Study of Force Induced by Probe Length Influenc...

引用

2024 IEEE International Conference on design, Test and Technology of Integrated Systems, dTTIS 2024

作者： Hermet, Cedric Favre, Luc Escoubas, Stephanie de Siena, Salvatore diperi, robert Aix Marseille Univ CNRS IM2NP EWS STMICROELECTRONICS Rousset Marseille France Aix Marseille Univ CNRS IM2NP Marseille France TECHNOPROBE R&D Department Italy EWS Process Probing STMICROELECTRONICS Rousset France

ISBN: (纸本)9798350363128

In the realm of semiconductor manufacturing, the electrical testing of pillar bump wafers is a critical step for ensuring device reliability and performance. This case study presents a comprehensive experimental investigation into the effects of force induced by probe tip length on the electrical test outcomes of pillar bump wafers at ambient temperature. Through a series of tests with different probe lengths, we assessed the impact of varying induced force on the variability of electrical contact and the degree of contamination accumulation on the probe surfaces. Our findings indicate a significant correlation between probe force induced by length and the consistency of electrical contact during testing. Shorter probe tips demonstrated higher contact force in response to progressive compression engendered by overdrive, with contamination accumulation. They were associated with reproductible and efficient electrical contact. Conversely, longer probe tips with lower contact force characteristics exhibited less contamination buildup, yet suffered from intermittent contact issues, potentially affecting test reliability. The study highlights the need for a balanced approach in probe use, weighing the benefits of contact stability against the drawbacks of contamination. The results serve as a guide for optimizing contact to enhance the accuracy and reliability of electrical tests on pillar bump wafers. These insights are expected to contribute to the development of improved testing protocols and equipment in the semiconductor industry. © 2024 IEEE.

关键词： Probes

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design and Modellization of a Neural Network used to Optimize and to Monitor a dC-dC converter 19

Design and Modellization of a Neural Network used to Optimiz...

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19th Conference on Ph.d research in Microelectronics and Electronics (PrIME)

作者： radhakrishnan, Sandeep Krishnan Nandialath Passi, Stefano Cabrini, Alessandro d'Angelo, Francesco Nicolosi, Alessandro Iannelli, Luca Univ Pavia Dept Ind & Informat Engn STMicroelect Pavia PV Italy STMicroelectronics Smart Power R&D Agrate Brianza MB Italy Univ Pavia Dept Ind & Informat Engn Pavia PV Italy

ISBN: (纸本)9798350386301;9798350386318

The purpose of this paper is to describe the model and the design of a neural network (NN) that optimizes a dC-dC converter power management system. The dC-dC converter plays a crucial role in maintaining the output voltage within the desired range. However, the conventional power management system has limitations in handling nonlinearities and uncertainties in the system. The proposed approach exploits the capability of a NN to accurately estimate certain parameters of the circuit that are closely associated with the functionality of the feedback control loop. In the case under analysis, we use Proportional-Integral-derivative (PId) control to regulate the output voltage. Precise estimation of the real value of analog components involved in the computation of PId parameters can improve the control loop and overall performance. Moreover, estimation of parasitic resistances of capacitors and inductors provides information about the functional state of the dC-dC converter and forecasting future fails.

关键词： Neural network power management estimation prevision failure optimization feedback monitoring

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