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作者： Herb Huang MEMS & TSV Technology Development Corporate R&D Center

An industry-wide trend has become evident in recent years that the rapid deployment of MEMS system products into mobile phones and consumer electronics generates the paramount driving force from evolution to revolution in manufacturing efficiency as well as supply chain and cost structures besides beside continuous improvement in product design and *** "CMOS-MEMS" is no doubt recognized widely as the central scene of future advance and growth the MEMS industry, while implicating even a broad and profound stretch again from the Moore's Law.

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determination Factors of Strain-relaxed Complex domain Structure observed in Thick Epitaxial pb(Zr,Ti)O3Films

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MrS Online Proceedings Library (OPL) 2011年第1期1199卷 1199-F08-08-1199-F08-08页

作者： Hiroshi Nakaki Satoru Utsugi Takashi Fujisawa Mitsumasa Nakajima Yoshitaka Ehara Tomoaki Yamada Hitoshi Morioka Toshihiro Ifuku Hiroshi Funakubo nakaki.h.aa@titech.ac.jp Tokyo Institute of Technology Innovative and Engineered Materials Yokohama Japan utsugi.s.aa@m.titech.ac.jp Tokyo Institute of Technology Innovative and Engineered Materials Yokohama Japan fujisawa.t.ac@m.titech.ac.jp Tokyo Institute of Technology Innovative and Engineered Materials Yokohama Japan nakajima.m.ac@m.titech.ac.jp Tokyo Institute of Technology Innovative and Engineered Materials Yokohama Japan ehara.y.aa@m.titech.ac.jp Tokyo Institute of Technology Innovative and Engineered Materials Yokohama Japan yamada.t.al@m.titech.ac.jp Tokyo Institute of Technology Innovative and Engineered Materials Yokohama Japan hitoshi.morioka@bruker-axs.jp Tokyo Institute of Technology Innovative and Engineered Materials Yokohama Japan Ifuku.toshihiro@canon.co.jp Canon Inc. Nano materials Technology Development Center Corporate R&D Headquarters Tokyo Japan funakubo.h.aa@m.titech.ac.jp Tokyo Institute of Technology Innovative and Engineered Materials Yokohama Japan

Crystal structure change with the temperature was investigated for 3 m-thick (100)/(001)-oriented epitaxial PbTiO3 films grown on SrTiO3 substrates. Complex strain-relaxed domain structure labeled as Type III was observed and directly transformed to the cubic phase at about 490°C. This transition temperature and the lattice parameter (a and c- axes) change with the temperature well agreed with the reported data for the PbTiO3 powders. The volume fraction of the (001) orientations, Vc, was almost independent of the temperature up to the phase transition temperature. The tilting angles of the spots in Xrd plan view were almost the same with the estimated ones from the lattice parameters and the Vc. This suggests that the angle of the domains identified by the domain structure in Type III. This structure is mainly determined by the tetragonality, (c/a ratio) and the Vc.

关键词： ferroelectricity piezoelectric thin film

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Multiphysics modeling of PCM devices for scaling investigation

Multiphysics modeling of PCM devices for scaling investigati...

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International Conference on Simulation of Semiconductor Processes and devices (SISPAd)

作者： G. Ferrari A. Ghetti d. Ielmini A. redaelli A. Pirovano Politecnico di Milano Milan Italy R&D Technology Development Numonyx Agrate-Brianza Italy

A multiphysics model for Phase Change Memory (PCM) is calibrated on a large set of experimental data. Critical material and interface properties such as electrical and thermal resistivities and their dependence on temperature are extracted from data or fitting electrical characteristics with numerical simulations. The model is shown to match with a unique set of parameters experimental data from 90 nm and 45 nm technology nodes. The calibrated model is then exploited to perform a sensitivity analysis of key cell characteristics to geometry and material properties variations. Furthermore, the model is used to predict performance of a scaled down cell suitable for the 32 nm technology node and the results demonstrate the consistent scalability of PCM with respect to the technology node.

关键词： resistance Conductivity Numerical models resistance heating Phase change materials Electrical resistance measurement

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Palladium incorporated nickel silicide for a cost effective alternative salicide technology for scaled CMOS

Palladium incorporated nickel silicide for a cost effective ...

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International Symposium on VLSI technology, Systems and Applications

作者： Yoshifumi Nishi Takeshi Sonehara Akira Hokazono Shigeru Kawanaka Satoshi Inaba Atsuhiro Kinoshita Advanced LSI Technology Laboratory Corporate R&D Center Toshiba Corporation Japan Center for Semiconductor Research and Development Toshiba Corporation Semiconductor Company Japan Device and Process Development Center Corporate R&D Center Toshiba Corporation Yokohama Japan

Incorporation of platinum (Pt) into nickel silicide (NiSi) improves the reliability and thermal stability of electrodes in Si MOSFETs. Increasing the Pt content is desirable for further scaled CMOS, but incorporation of more Pt would tremendously increase the material cost. In addition, since Pt is one of the key materials for eco-technology such as catalyst for exhaust absorption and so on, reduction of the use of Pt whose amount is limited is essential for ecology. recently palladium (Pd), which has similar chemical properties to those of Pt, has been attracting interest as a substitute of Pt. Several works have pointed out that NiPdSi bulk film has superior thermal stability to NiSi. However, its potentiality in fully integrated CMOS devices has not been studied yet. In this work, we investigate the detailed properties of NiPdSi on fully integrated CMOS structures fabricated with the advanced process technology as a candidate of the alternative silicide material for NiPtSi.

关键词： CMOS technology Palladium Nickel Silicides Costs Thermal stability Platinum Electrodes MOSFETs Absorption

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Functional and Performance Verification of Overlay Multicast Applications - A Product Level Approach

Functional and Performance Verification of Overlay Multicast...

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Consumer Communications and Networking Conference, CCNC IEEE

作者： Thilmee Baduge Lim Boon Ping Kunio Akashi Jason Soong Ken-ichi Chinen Ettikan K. K. Eiichi Muramoto Immersive Communication Task Force Panasonic Corporation Japan Advanced Technology Development Group Panasonic R&D Center Malaysia Japan Advanced Institute of Science and Technology Japan

In this paper we present a testbed for the functional and performance verification and validation of product level overlay multicast (or ALM in short) applications which is a complex task due to humongous test patterns. Structured, systematic and simplified test environment is vital for product level quality validation. The key features of this testbed are network emulation, automated test scenario execution, log collection and testbed/real environment interconnectivity. The testbed uses StarBEd as its mother testbed and netem as the network emulator. The key contributions of this work are calibration of netem in term of network emulation and establishing an architecture to use netem and StarBEd for ALM system verification. The calibration of netem was carried out up to 30 pipes (logical links) and the results show the network emulation can be done at maximum 1.2% packet loss. One of the simple ALM verification experiments executed on the testbed took only 43 hours for execution completion compared to human execution which would take 15 weeks.

关键词： Automatic testing Emulation Calibration Protocols Network topology Switches Communications Society System testing Humans Peer to peer computing

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Comparison of Two Kinds of Humidifier on Microorganism Transmission via Aerosol of different Size and Quantity

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American Journal of Infection Control 2011年第5期39卷 E191-E191页

作者： Hongchao Wang Baomin Chen Yinghong Wu Qing Yang R&D center Beijing Orient-Tide Science and Technology Development Co. Ltd. Beijing China Director Infection Control Dept. Beijing Di-Tan Hospital Beijing China Director of Beijing Nosocomial Infection Control Network Peking University People's Hospital Beijing China Chief Researcher Dept. of Toxicology Beijing CDC P.R. China Beijing China

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reliability constraints for TANOS memories due to alumina trapping and leakage

Reliability constraints for TANOS memories due to alumina tr...

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Annual International Symposium on reliability Physics

作者： Salvatore M. Amoroso Aurelio Mauri Nadia Galbiati Claudia Scozzari Evelyne Mascellino Elisa Camozzi Armando rangoni Tecla Ghilardi Alessandro Grossi Paolo Tessariol Christian Monzio Compagnoni Alessandro Maconi Andrea L. Lacaita Alessandro S. Spinelli Gabriella Ghidini R&D Technology Development Numonyx Agrate-Brianza Milan Italy Dipartimento di Elettronica e Informazione Politecnico di Milano and IUNET Milan Italy IFN-CNR Milan Italy

In this work we present a detailed investigation of TANOS memory reliability, focusing on issues raised by Al 2 O 3 trapping/detrapping and leakage. These effects are investigated as a function of alumina thickness, electric field and temperature, comparing experimental and modeling results for trap parameters extraction. For TANOS devices, Al 2 O 3 charge storage modifies program and erase saturation level particularly when higher Al 2 O 3 thikness are considered. Threshold instability in early steps for endurance and retarded behavior for retention can be also ascribed to the Al 2 O 3 trapping. Moreover, Al 2 O 3 layer has been shown to provide the main leakage path for bottom oxides thickness in the 4.5 nm or above range.

关键词： Memory management Stress High-K gate dielectrics Nonvolatile memory Electron traps Capacitors research and development Temperature Parameter extraction Semiconductor device modeling

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Investigation of the threshold voltage instability after distributed cycling in nanoscale NANd Flash memory arrays

Investigation of the threshold voltage instability after dis...

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Annual International Symposium on reliability Physics

作者： Christian Monzio Compagnoni Carmine Miccoli riccardo Mottadelli Silvia Beltrami Michele Ghidotti Andrea L. Lacaita Alessandro S. Spinelli Angelo Visconti Dipartimento di Elettronica e Informazione Politecnico di Milano and IUNET Milan Italy R&D-Technology Development Numonyx Agrate-Brianza Milan Italy IFN-CNR Milan Italy

This paper presents a detailed experimental investigation of the cycling-induced threshold voltage instability of deca-nanometer NANd Flash arrays, focusing on its dependence on cycling time and temperature. When the array is brought to a programmed state after cycling, instability mainly shows up as a negative shift of its threshold voltage cumulative distribution, increasing with time and resulting from partial recovery of cell damage created in the previous cycling period. The threshold voltage loss displays a strong dependence not only on the tunnel oxide electric field during retention, but also on the cycling conditions. In particular, performing cycling over a longer time interval or at higher temperatures delays the threshold voltage transients on the logarithmic time axis. The delay factor is studied as a function of the cycling duration and temperature on 60 and 41 nm technologies, extracting the parameter values required for a universal damage-recovery metric for NANd.

关键词： Threshold voltage Temperature dependence delay effects Flash memory Testing research and development Paper technology displays Semiconductor device reliability Semiconductor device modeling

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A concept of a novel edge termination technique: Junction termination (rJT)

A concept of a novel edge termination technique: Junction te...

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International Symposium on Power Semiconductor devices and Ics (ISPSd)

作者： Shigeto Honda ryoich Fujii Tsuyoshi Kawakami Seiji Fujioka Atsushi Narazaki Kaoru Motonami Power Semiconductor Device Development Department Mitsubishi Electric Corporation Limited Koshi Kumamoto Japan Power Semiconductor Device Development Department Manufacturing Engineering Center Mitsubishi Electric Corporation Limited Koshi Kumamoto Japan Power Semiconductor Device Development Department Advanced technology R&D center Mitsubishi Electric Corporation Limited Koshi Kumamoto Japan

ISBN: (纸本)9781424477180

This paper presents a novel junction termination technique, named recess Junction Termination (rJT), for power devices. This new junction termination improves the breakdown voltage of a planar junction by a silicon recess located to create a positive bevel, which reduces the peak of electric field. The rJT can reduce a thermal budget for the rESUrF (rEduced SUrface Field) layer by the silicon recess, and has compatibility with a fine-pitch process due to a planarization process using Chemical Mechanical Polish (CMP) treatments. After numerous simulations to optimize the structure parameters, we have succeeded in obtaining sufficient blocking capabilities of pn-rJT-diodes, the voltage ratings of which are from 75 V to 1700 V.

关键词： Silicon Planarization Boron Voltage Substrates Power semiconductor devices Power engineering and energy Surface treatment Fabrication Costs

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A boost in research on slags: a doubling in publications from literature since 2003

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Ironmaking & Steelmaking 2010年第7期37卷 476 - 481页

作者： r. Boom S. riaz K. C. Mills Director R&D Strategy & Competence Corus Research Development & Technology IJmuiden Technology Centre PO Box 10000 1970 CA IJmuiden The Netherlands Professor NIMR Chair in Primary Metals Production Department of Materials Science and Engineering Mekelweg 2 2628 CD Delft The Netherlands Email: Knowledge Group Leader Corus Research Development & Technology Teesside Technology Centre Grangetown Middlesbrough TS6 6US United Kingdom Email: Professor Imperial College Department of “Materials Prince Consort Rd London SW7 2BP United Kingdom Email:

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