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Symposium on VLSI technology

作者： S.Y. Lee H.H. Kim d.J. Jung Y.J. Song N.W. Jang M.K. Choi B.K. Jeon Y.T. Lee K.M. Lee S.H. Joo S.O. Park K. Kim Technology Development Team R&D Center Memory Division Samsung Electronics Company Limited South Korea

ISBN: (纸本)4891140127

recently, technology innovation for high density and high performance FrAM has been pronounced. Among the breakthrough technologies for high density and high performance FrAM, 1T1C capacitor-on-bitline (COB) cell technology is essential because it can greatly reduce FrAM cell size compared to previous and current 2T2C FrAMs (Kinam Kim, 1999; Lee et al., 1999). design improvement for enhanced sensing ability is also a promising technology for highly reliable mega-bit density FrAM (Jeon et al, 2000). Although the recent demonstration shows a promising future for stand-alone FrAM applications, current 1T1C COB FrAM still has incomparably large cell size factor compared to drAM and flash. This is one of the most challenging issues that FrAM faces for developing high-density stand-alone memory. In this work, a novel cell structure for sub-10 F/sup 2/ cell size is for the first time developed. The key technologies for the sub-10 F/sup 2/ novel cell are: (1) advanced oxidation barrier and PZT film technologies which enables MIM ferroelectric capacitors to be lowered to /spl sim/500 nm thick stack: (2) single-mask capacitor etching technology which can produce >80/spl deg/ ferroelectric capacitor fence slope; (3) no cell via contact technology by which capacitor pitch can ideally be reduced to 2F; (4) an Al-reflow process which enables sub-0.4 /spl mu/m back-end interconnection without degrading the ferroelectric capacitor. The novel cell is demonstrated with an experimental 4 Mb FrAM, where the 1T1C COB cell is fabricated with folded bit line architecture and plate line-up sensing scheme.

关键词： random access memory Ferroelectric films Nonvolatile memory Plugs Ferroelectric materials MIM capacitors Tin Electrodes Oxidation Etching

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SAdS: A new component of Fas-dISC is the accelerator for cell death signaling and is downregulated in patients with colon carcinoma (retraction of vol 7, pg 88, 2001)

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NATUrE MEdICINE 2001年第6期7卷 749-749页

作者： Suzuki, A Obata, S Hayashida, M Kawano, H Nakano, T Shiraki, K Project for the Cell Death Research Basic Technology Research Laboratory Daiichi Pharmaceutical Co. Ltd. Tokyo R&D Center Kitakasai 1-16-13 Edogawa-ku Tokyo 134-8630 Japan Biochemical Laboratory Research & Development Group Kishida Chemical Co. Ltd. Sanda Factory Techno-Park 14-10 Sanda Hyogo 669-1339 Japan Project for the Cell Death Research Basic Technology Research Laboratory Daiichi Pharmaceutical Co. Ltd. Tokyo R&D Center Kitakasai 1-16-13 Edogawa-ku Tokyo 134-8630 Japan Project for the Cell Death Research Basic Technology Research Laboratory Daiichi Pharmaceutical Co. Ltd. Tokyo R&D Center Kitakasai 1-16-13 Edogawa-ku Tokyo 134-8630 Japan The First Department of Internal Medicine Mie University School of Medicine Edobashi 2-174 Tsu Mie 514-8507 Japan The First Department of Internal Medicine Mie University School of Medicine Edobashi 2-174 Tsu Mie 514-8507 Japan

Fas is the death receptor, transducing cell death signaling upon stimulation by Fas ligand. during Fas-initiated cell death signaling, the formation of Fas-death inducing signaling complex (Fas-dISC) is the first step. Here we have identified a new component of Fas-dISC which we call 'small-accelerator for death signaling' (SAdS). SAdS cdNA encodes a 150 amino acid polypeptide (Mr = 16,700). during Fas-mediated cell death, SAdS enhances the interaction of Fas-death domain-interactive factors (FAdd) and procaspase-8, and deletion mutant analysis has identified FAdd- and caspase-8-interactive domains in SAdS. Inhibition or removal of SAdS delays Fas-mediated cell death. In addition, we demonstrate the deletion or mutation of SAdS in patients with colon carcinoma and that exogenous SAdS expression in human colon carcinoma SW480 cells that lack SAdS leads to re-acquisition of Fas-mediated cell death. Here, we propose that SAdS is one of the cell death-associated factors and enhances Fas-dISC formation, especially FAdd and procaspase-8 recruitment.

关键词： down-regulation Signal Transduction Antigens Cd95 Apoptosis Base Sequence Caspases Colonic Neoplasms dNA Primers Humans Protein Binding

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Feasibility study for recycling of JVC compact discs for use in the manufacturing of Motorola plastic housings

Feasibility study for recycling of JVC compact discs for use...

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International Symposium on Environmentally Conscious design and Inverse Manufacturing (Ecodesign)

作者： M. Stutz d. Schnecke T. Takahashi N. Kawai K. Tsujita MATC Europe Motorola Advanced Technology Center Europe Wiesbaden Germany Technology Development Division (Kurihama R&D Center) Victor Company of Japan Limited Yokosuka Kanagawa Japan

ISBN: (纸本)0769512666

In a joint research project between JVC Kurihama r&d Center and Motorola Advanced technology Center-Europe the recycling of JVC compact discs (Cds) for use in the manufacturing of Motorola plastic housings was developed and evaluated. returned Cds, made out of polycarbonate (PC), can potentially be used to mold housings of electronic products, also made out of PC. Closing the PC loop is not only technically feasible, but also a gain for the environment, reducing the resource and energy consumption comparing virgin versus recycled PC. To allow returned Cds to be processed into plastic housings, Cds have to be decoated of the aluminum layer, the lacquer and the label ink in order to serve as input material for producing recycled PC. Then the clear Cds are crushed, blended with virgin PC and pelletized to obtain defined material properties. The JVC Kurihama r&d Center developed decoating methods for returned Cds, based on extensive trials using mechanical and chemical decoating techniques, resulting in clean Cd parts. The material properties of the plastic recyclate was tested and specified. After evaluating the promising test results by JVC Kurihama r&d Center on the recycled PC material, the Motorola Advanced technology Center-Europe decided to run a trial mold of an actual housing at a molder in Germany. A two-way mobile radio cover was molded with recycled Cd material. The material properties of the original versus recycled resin were evaluated. The cover made with recycled Cds was put through an ALT (Accelerated Life Test), yielding in more information on the possibilities to use recycled material. The joint research project shows that a high tech product such as the Cd can serve as a basis for housings of electronic and electrical equipment after its useful life. With a sophisticated technology the PC loop is closed, benefiting ecology and economy.

关键词： recycling Plastics Material properties Materials testing Manufacturing Energy consumption Aluminum Lacquers Ink Chemicals

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Highly reliable interconnect integration of Cu and low-k organic polymer based on fine Cd controls

Highly reliable interconnect integration of Cu and low-k org...

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IEEE International Conference on Interconnect technology

作者： Y. Nishioka S. Tomohisa Y. Toyoda T. Fukada T. Satake M. Matsuura S. domae A. Ohsaki ULSI Development Center Mitsubishi Electric Corporation Limited Itami Hyogo Japan Advanced Technology R&D Center Mitsubishi Electric Corporation Limited Amagasaki Hyogo Japan ULSI Process Technology Development Center Matsushita Electronics Corporation Kyoto Japan

ISBN: (纸本)0780366786

A Cu dual damascene interconnect with a low-k organic polymer was fabricated and Cd changes of its vias and trenches were investigated. By means of optimizing both the SiO/sub 2/ etching condition and the SiN thickness in a stacked hard mask, Cd changes of trenches from a designed pattern size to the final one were suppressed up to about 10 nm. As a result, electrical properties were controlled and kept close to calculated values from the designed pattern size. This synthetic process integration based on the fine Cd control technique is promising for the realization of a fine dual damascene interconnect of 0.13-/spl mu/m and further technology node.

关键词： Etching Silicon compounds Ultra large scale integration dielectric materials Fabrication Polymer films Size measurement resists research and development design optimization

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CMOS low-noise/driver MMIC amplifiers for 2.4-GHz and 5.2-GHz wireless applications

CMOS low-noise/driver MMIC amplifiers for 2.4-GHz and 5.2-GH...

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Topical Meeting on Silicon Monolithic Integrated Circuits in rF Systems

作者： K. Yamamoto T. Heima A. Furukawa M. Ono Y. Hashizume H. Komurasaki H. Sato N. Kato System LSI Development Center Mitsubishi Electric Corporation Limited Itami Hyogo Japan Advanced Technology R&D Center Mitsubishi Electric Corporation Limited Itami Hyogo Japan Information Technology R&D Center Mitsubishi Electric Corporation Limited Itami Hyogo Japan System LSI Division Mitsubishi Electric Corporation Limited Itami Hyogo Japan

This paper describes two kinds of on-chip matched low-noise/driver MMIC amplifiers (LN/d-As) suitable for 2.4 GHz and 5.2 GHz short-range wireless applications. The successful use of the current-reuse topology and interdigitated capacitors (IdCs) enables sufficiently low-noise and high output power operations with low current dissipation despite the chip fabrication in a standard bulk CMOS leading to large rF substrate losses. The main measurement results of the two LN/d-As are as follows: a 3.8 dB noise figure (NF) and a 10.1 dB gain under conditions of 1.8 V and 6 mA, a 3.4 dBm 1 dB gain compressed output power (P/sub 1dB/) at 2.4 V and 13 mA for the 2.4-GHz LN/d-A, and a 4.9 dB NF and a 11.1 dB gain with a 1.8 V and 10 mA supply, a 2.3 dBm P/sub 1dB/ at 2.4 V and 16 mA for the 5.2 GHz LN/d-A.

关键词： driver circuits MMICs Low-noise amplifiers Noise measurement Gain Power generation radiofrequency amplifiers Topology Capacitors Power amplifiers

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A 700 V lateral power MOSFET with narrow gap double metal field plates realizing low on-resistance and long-term stability of performance

A 700 V lateral power MOSFET with narrow gap double metal fi...

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International Symposium on Power Semiconductor devices and Ics (ISPSd)

作者： N. Fujishima M. Saito A. Kitamura Y. Urano G. Tada Y. Tsuruta Devices Technology Laboratory Fuji Electric Corporate Research and Development Limited Matsumoto Nagano Japan Semiconductor Device R&D Center Fuji EIectric Company Limited Matsumoto Nagano Japan

ISBN: (纸本)4886860567

A 700 V lateral power MOSFET with a narrow gap double metal field plate structure is proposed. The MOSFET exhibits an improved specific on-resistance of 26 /spl Omega/ mm/sup 2/ and achieves extremely stable performance under long-term high-voltage operation. A power IC, which integrates the developed MOSFET using 1 /spl mu/m CMOS process, has successfully been applied to AC to dC converters in portable appliances.

关键词： MOSFET circuits Power MOSFET FETs research and development dC-dC power converters Passivation Stability Laboratories Semiconductor devices Power integrated circuits

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Backend Process for Cylindrical ru/Ta2O5/ru Capacitor for Future drAM

Backend Process for Cylindrical Ru/Ta2O5/Ru Capacitor for Fu...

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2001 6～(th) International Conference on Solid-State and Integrated Circuit technology

作者： J.Lin T.Suzuki H.Minakata A.Shimada K.Tsunoda M.Fukuda T.Kurahashi Y.Fukuzumi A.Hatada A.Sato P.H.Sun Y.Ishibashi H.Tomita N.Nishikawa E.Ito W.C.Liu C.M.Chu r.Suzuki M.Nakabayashi d.Matsunaga K.Hieda K.Hashimoto S.Nakamura Y.Kohyama C.M.Shiah Technology Development Division Fujitsu Limited Technology Development Division Fujitsu Limited Fujitsu Laboratories Limited Technology Development Division Fujitsu Limited Fujitsu Laboratories Limited Fujitsu Laboratories Limited Fujitsu Laboratories Limited Memory LSI R&D Center Toshiba Corporation Fujitsu Laboratories Limited Fujitsu Laboratories Limited DRAM Process Integration and Module Technology Department Winbond Electronics Corporation Memory LSI R&D Center Toshiba Corporation Process&Manufacturing Engineering Center Toshiba Corporation Technology Development Division Fujitsu Limited Process&Manufacturing Engineering Center Toshiba Corporation DRAM Process Integration and Module Technology Department Winbond Electronics Corporation DRAM Process Integration and Module Technology Department Winbond Electronics Corporation Fujitsu Laboratories Limited Technology Development Division Fujitsu Limited Technology Development Division Fujitsu Limited Process&Manufacturing Engineering Center Toshiba Corporation Technology Development Division Fujitsu Limited Fujitsu Laboratories Limited Memory LSI R&D Center Toshiba Corporation DRAM Process Integration and Module Technology Department Winbond Electronics Corporation

A novel backend process is developed for thecylindrical ru/TaO/ru capacitor for 130nm generationdrAMs to achieve good electrical *** gas（3%H/97%N）anneal（FGA） induceddegradation can be effectively *** thecylindrical ru/TaO/ru capacitor with full backendprocesses,including passivation layer formation and aFGA,the cell leakage current and cell capacitance are1fA（at±0.8V at 85℃）and 15fF,respectively.

关键词： Backend Process for Cylindrical ru/Ta2O5/ru Capacitor for Future drAM FGA

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Inverter miniaturizing technologies for EV/HEV applications

Inverter miniaturizing technologies for EV/HEV applications

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IEEE International Vehicle Electronics Conference

作者： Y. Kuramoto H. Maekawa G. Majumdar K.H. Hussein T. Kikunaga T. Okuda Mitsubishi Electric Automotive Electronics Development Center Himeji Japan Mitsubishi Electric Power Device Division Himeji Japan Fukuryo Semicon Engineering Corporation Mitsubishi Electric Advanced Technology R&D Center Himeji-city Hyogo-ken Japan

ISBN: (纸本)0780372298

In this paper, an integrated intelligent power drive unit (IPU) is introduced as the next generation electric power module and inverter for EV/HEV. The IPU designs are based on new concepts to achieve a very compact overall structure, high reliability, high functionality and high efficiency. At first, the technologies to miniaturize the inverter are introduced and the benchmarks between the current inverter system using IPM (intelligent power module) and using IPU are shown. Finally, to verify the validity of IPU design, experimental data are shown.

关键词： Inverters Hybrid electric vehicles Insulated gate bipolar transistors Power system reliability Voltage Semiconductor diodes Automotive engineering Intelligent structures Intelligent vehicles Multichip modules

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A 99-mm/sup 2/, 0.7-W, single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mbit embedded drAM for portable 422P@HL encoder system

A 99-mm/sup 2/, 0.7-W, single-chip MPEG-2 422P@ML video, aud...

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Custom Integrated Circuits Conference (CICC)

作者： S. Kumaki H. Takata Y. Ajioka T. Ooishi K. Ishihara A. Hanami T. Tsuji Y. Kanehira T. Watanabe C. Morishima T. Yoshizawa H. Sato S. Hattori A. Koshio K. Tsukamoto T. Matsumura System LSI Development Center Mitsubishi Electric Corporation Limited Japan System LSI Division Mitsubishi Electric Corporation Limited Japan ULSI Development Center Mitsubishi Electric Corporation Limited Itami Hyogo Japan Information Technology R&D Center Mitsubishi Electric Corporation Limited Kamakura Kanagawa Japan ULSI Process Technology Development Center Semiconductor Company Matsushita Electronics Corporation Kyoto Japan

ISBN: (纸本)0780365917

A scalable single-chip 422P@ML MPEG-2 video, audio, and system encoder LSI for portable 422P@HL system is described. The encoder LSI is implemented using 0.13 /spl mu/m embedded drAM technology. It integrates 3-M logic gates and 64-Mbit drAM in an area of 99-mm/sup 2/. The power consumption is suppressed to 0.7-Watts by adopting a low power drAM core. It performs real-time 422P@ML video encoding, audio encoding, and system encoding with no external drAM. Furthermore, the encoder LSI realizes a 422P@HL video encoder with multi-chip configuration, due to its scalable architecture. This results in a PC-card size 422P@HL encoder with lowest power consumption for portable HdTV codec system.

关键词： random access memory Encoding Large scale integration HdTV digital filters Nonlinear filters Ultra large scale integration Energy consumption real time systems Costs

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Experimental Evaluation of reconfigurable Brachiating Space robot

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Journal of robotics and Mechatronics 2001年第5期13卷 548-553页

作者： Hayashi, ryoichi Matunaga, Saburo Ohkami, Yoshiaki Mechanical and Aerospace Engineering Tokyo Institute of Technology 2-12-1 O-okayama Meguro-ku Tokyo152-8552 Japan Tsukuba Space Center R&D Division National Space Development Agency of Japan 2-1-1 Sengen Tsukuba-shi Ibaraki-ken305-8505 Japan

We developed a reconfigurable brachiating space robot (rBr) based on modularized design, cable reduction, and distributed control able to move over KIBO (Japanese experimental module) of the International Space Station in a brachiating manner and to reconfigure its arms based on task requirements. This paper presents rBr capabilities, focusing on grasping handrails and reconfiguration. We conduct experiments to evaluate rBr brachiation and reconfiguration and present results. © Fuji technology Press Ltd.

关键词： Space stations

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