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Symposium on VLSI Circuits

作者： T. Nakura K. Ueda K. Kubo W. Fernandez Y. Matsuda K. Mashiko System LSI Development Center Mitsubishi Electric Corporation Limited Itami Hyogo Japan Information Technology R&D Center Mitsubishi Electric Corporation Limited Itami Hyogo Japan ULSI Development Center Mitsubishi Electric Corporation Limited Itami Hyogo Japan

This paper describes a 16:1 multiplexer (MUX) using a 0.18 /spl mu/m partially-depleted SOI-CMOS technology. Owing to a selector type architecture with a pipeline structure as well as small junction capacitances of SO... 详细信息

关键词： Multiplexing Circuits Timing Capacitance CMOS technology Pipelines Clocks delay effects Frequency Large scale integration

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Low resistance Co-salicided 0.1 /spl mu/m CMOS technology using selective Si growth

Low resistance Co-salicided 0.1 /spl mu/m CMOS technology us...

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Symposium on VLSI technology

作者： H. Sayama S. Shimizu Y. Nishida T. Kuroi Y. Kanda M. Fujisawa Y. Inoue T. Nishimura T. Oishi T. Nakahata T. Furukawa S. Yamakawa Y. Abe S. Maruno Y. Tokuda S. Satoh ULSI Dev. Center Mitsubishi Electr. Corp. Hyogo Japan ULSI Development Center Mitsubishi Electric Corporation Limited Itai Hyogo Japan Advanced Technology R&D Center Mitsubishi Electric Corporation Limited Itai Hyogo Japan

A low resistance salicided 0.1 /spl mu/m CMOSFET has been developed with precisely controlled T-shaped gate and optimum gate structure for thick CoSi/sub 2/. Selective Si growth (SSG) using a SiO/sub 2/-SiN stacked sidewall with the exposed SiN top hill enables suppression of junction leakage for thick Co silicidation, to eliminate bridging between gate and source/drain (S/d), and to precisely control the extra gate length for T-shaped gates. Moreover, the nitrogen profile in the p/sup +/ gate is optimized to suppress gate depletion induced by the thick Co. Since a heavily nitrided gate oxide insulator and N implantation of the poly-Si surface can prevent gate-implanted B ions from being diffused into the substrate and into the CoSi/sub 2/ layer, an increase in the gate sheet resistance, B penetration, and gate depletion can be simultaneously resolved, and thus high performance 0.1 /spl mu/m CMOS can be achieved with gates of as low as 1.9 /spl Omega//sq. sheet resistance.

关键词： CMOS technology Silicon compounds Insulation Surface resistance doping Paper technology Space technology Voltage Silicides Very large scale integration

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Barrier properties of Ta–ruO2 diffusion barrier for dynamic random access memory capacitor bottom electrodes

Journal of Vacuum Science & Technology B: Microelectronics a...

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Journal of Vacuum Science & technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena 1999年第4期17卷 1470-1476页

作者： dong-Soo Yoon Hong Koo Baik Sung-Man Lee Sang-In Lee Department of Metallurgical Engineering Yonsei University Seoul 120-749 Korea Department of Materials Engineering Kangwon National University Chuncheon Kangwon-Do 200-701 Korea Development of Technology Semiconductor R&D Center Samsung Electronics Co. San#24 Nongseo-Lee Kiheung-Eup Yongin-City Kyungki-Do 449-900 Korea

We proposed the Ta–ruO2 diffusion barrier for oxygen in the dynamic random access memory capacitor bottom electrode, and investigated the barrier and electrical properties of the developed diffusion barrier. The Ta–ruO2/TiSi2/poly-Si/SiO2/Si contact system deposited with and without the SiO2 capping layer showed the lower total resistance and ohmic characteristics up to 800 °C. For the Ta–ruO2/TiSi2/poly-Si/SiO2/Si contact system, no other phases observed except for the formation of conductive ruO2 phase in the barrier film by reaction with the indiffused oxygen after annealing in air, but the thin oxidized layer at the Ta–ruO2/TiSi2 interface was formed by external oxygen. However, a large number of the crystallites in the annealed samples compared to that of as-deposited film were observed even after depth profile. The crystallites consisted of ru and O containing a small amount of Ta. In addition, the embedded ruO2 crystalline phase was observed in the thin oxidized TiSi2 surface layer. Correspondingly, we suggest that the ohmic mechanism of the Ta–ruO2/TiSi2/poly-Si/SiO2/Si contact system is an embedded ruO2 crystalline phase involving a small amount of Ta in a Ta amorphous structure.

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0.1 /spl mu/m level contact hole pattern formation with KrF lithography by resolution enhancement lithography assisted by chemical shrink (rELACS)

0.1 /spl mu/m level contact hole pattern formation with KrF ...

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International Electron devices Meeting (IEdM)

作者： T. Toyoshima T. Ishibashi A. Minanide K. Sugino K. Katayama T. Shoya I. Arimoto N. Yasuda H. Adachi Y. Matsui Advanced Technology R&D Center Mitsubishi Electronic Corporation Amagasaki Hyogo Japan ULSI Development Center Mitsubishi Electronic Corporation Itami Hyogo Japan Ryoden Semiconductor System Engineering Corporation Itami Hyogo Japan

We developed a hole shrink process named rELACS (resolution Enhancement Lithography Assisted by Chemical Shrink) that is a robust and low-cost method. This method makes use of crosslinking reaction between the materials coated on the resist pattern, and the acid existing at the resist wall. By the rELACS, we could shrink KrF resist hole patterns to 0.1 /spl mu/m level. The shrinkage of hole size is dependent on both baking temperature and initial hole size. This process has been established for the fabrication of 0.20 /spl mu/m devices.

关键词： Pattern formation Lithography resists Shape Size control Temperature dependence Chemical processes

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The best combination of aluminum and copper interconnects for a high performance 0.18 /spl mu/m CMOS logic device

The best combination of aluminum and copper interconnects fo...

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International Electron devices Meeting (IEdM)

作者： M. Igarashi A. Harada H. Amishiro H. Kawashima N. Morimoto Y. Kusumi T. Saito A. Ohsaki T. Mori T. Fukada Y. Toyoda K. Higashitani H. Arima ULSI Development Center Mitsubishi Electronic Corporation Itami Hyogo Japan Mitsubishi Denki Kabushiki Kaisha Chiyoda-ku Tokyo JP Advanced Technology R&D Center Mitsubishi Electronic Corporation Amagasaki Hyogo Japan

A high performance 0.18 /spl mu/m CMOS logic device has been developed with 0.15 /spl mu/m transistors and six-level interconnects. The multi-level interconnect system consists of a conventional process with Al wire and a dual damascene process with Cu wire. 4-level Al interconnects with fine metal pitch are suitable for short distance wiring such as intra block cell to cell interconnects, whereas 2-level Cu interconnects with coarse metal pitch are used for long distance wiring such as mega block to block interconnects to achieve high-speed and high-density LSI devices.

关键词： Aluminum Copper Wire Parasitic capacitance Wiring delay effects High-K gate dielectrics Logic devices Etching Oxidation

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Impact of nitridation engineering on microscopic SILC characteristics of sub-10-nm tunnel dielectrics

Impact of nitridation engineering on microscopic SILC charac...

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International Electron devices Meeting (IEdM)

作者： T. Ogata M. Inoue T. Nakamura N. Tsuji K. Kobayashi K. Kawase H. Kurokawa T. Kaneoka Y. Ohno H. Miyoshi ULSI Development Center Mitsubishi Electronic Corporation Itami Hyogo Japan Ryoden Semiconductor System Engineering Corporation Itami Hyogo Japan Memory IC Division Mitsubishi Electronic Corporation Itami Hyogo Japan Advanced Technology R&D Center Mitsubishi Electronic Corporation Amagasaki Hyogo Japan

We have statistically analyzed 28800 cells of arrayed stacked gate transistors, and, for the first time, we discuss the effectiveness of NO and N/sub 2/O nitridation in suppressing microscopic SILC (mSILC). We have found that NO nitridation is more effective in suppressing the mSILC than N/sub 2/O nitridation and is very promising for the reduction of bit failures.

关键词： Microscopy dielectric substrates MOS capacitors Electron traps Stress dielectric measurements Charge carrier processes dielectric films Leakage current Gases

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Least-hop path planning using neural networks

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Electronics and Communications in Japan (Part I: Communications) 1998年第8期80卷

作者： Haruko Kawahigashi Ken-ichi Tanaka Kazuyoshi Oshima Mitsubishi Electric Corp. Information Technology R&D Center Kamakura Japan 247 Advanced Technology R&D Center Amagasaki Japan 661 Information & Communication Systems Development Center Kamakura Japan 247

recently, application of neural networks using their parallel processing feature has progressed. This paper proposes a routing method using a neural network and based on dynamic programming. The proposed method finds the least-hop path between two points in a communication network. The method consists of the application of disturbance to the destination, propagation of the disturbance to the source, and search for the shortest path from the source to the destination, using the distribution of the influences of the disturbance at each node. © 1997 Scripta Technica, Inc. Electron Comm Jpn Pt 1, 80(8): 1–6, 1997

关键词： neural network broad band-ISdN network design network theory data communication network network technology

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Investigation of Pt/Ta diffusion barrier using hybrid conductive oxide (ruO2) for high dielectric applications

Journal of Vacuum Science & Technology B: Microelectronics a...

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Journal of Vacuum Science & technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena 1998年第3期16卷 1137-1141页

作者： dong-Soo Yoon Hong Koo Baik Sung-Man Lee Sang-In Lee Hyun ryu Hwack Joo Lee Department of Metallurgical Engineering Yonsei University Seoul 120-749 Korea Department of Materials Engineering Kangwon National University Chuncheon Kangwon-Do 200-701 Korea Technology Development Semiconductor R&D Center Samsung Electronics Co. San#24 Nongseo-Lee Kiheung-Eup Yongin-City Kyungki-Do 449-900 Korea New Material Evaluation Center KRISS Taejon 305-600 Korea

The Pt/Ta diffusion barrier using hybrid conductive oxide (ruO2) for dynamic random access memory and ferroelectric random access memory capacitor bottom electrodes is proposed. The thermal stability of Pt+ruO2 (50 nm)/Ta+ruO2 (50 nm)/TiSi2/poly-Si/SiO2/Si contact system is investigated and compared to that of the Pt(50 nm)/Ta(50 nm)/TiSi2/poly-Si/SiO2/Si contact system. The Pt+ruO2/Ta+ruO2/TiSi2/poly-Si/SiO2/Si contact system sustained its structure up to 650 °C, whereas Pt/Ta/TiSi2/poly-Si/SiO2/Si contact system was completely degraded after annealing at 650 °C. In the former case, the addition of ruthenium dioxide (ruO2) into the Pt bottom electrode layer led to retardation of the oxygen indiffusion, preventing the indiffusion of oxygen up to 650 °C. In addition, the Ta+ruO2 diffusion barrier showed an amorphous structure and ruO2 is bound to the Ta matrix, inhibiting the interdiffusion of O, Pt, and Si through grain boundaries which can act as fast diffusion paths up to high temperatures. Therefore, it appeared that the barrier properties of Pt/Ta diffusion barrier are improved by using hybrid conductive oxide (ruO2).

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recapitalizing the Navy through optimized manning and improved reliability

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NAVAL ENGINEErS JOUrNAL 1998年第6期110卷 61-72页

作者： Anderson, dE Malone, TB Baker, CC Mr. David E. Anderson:is a Navel Engineer with the Naval Sea Systems Command where he is currently assigmd to the HumanSystems Integration branch. Mr Anderson has a Bachelor of Science degree an Environmental Engineering from Flurida Technological University and a Master's in Environmental Engiwering from the University of Central Flurida. He currentEy is an HSI manager for a number oflvay R&D and skig acquisition efforts. Dr. Thomas B. Malone:received a Ph.D. in Experimental Psychology from Fordham University in 1964. He is President of Carlow International Incorporated an organization dedicated to human factors research and development with emphasis an mantime systems. He has directed over 350 programs and projects in his 33 year career and is responsible for overall management of all contract programs within the Corporation. He is a Past President of the Human Factors and E r g m i c s Society (HFES) of which he is a Fellow. He is also a Fellow of the Washington Academy of Sciences He was selected as a member of the N A S Space Sciences Technical Advisuiy Committee on Technoloo Requirements for Human Performance on Long Duration Space Missions in 2989 and 90. He was elected as the First Chair of the Systems Development Technical Group of the HFES. Dr Malone is currently managing eflorts to devehp and auto- mate standardized processes for canducting human systems integration (HSI) in the military weapon systems acquisition process and fov developing automated tools to facilitate fledormance of specific steps in the HSI process. Dr Malone also is currently occupied in applying human engineering to the DD 21 and is serving as the Chair ofthe System ManninglHuman Perfomzance Working IPT under the DD 21 ManninglHSI IPT chaired ty PMS 500M. Mr. Clifford Baker:has over 20 years experience in developing and applying human factors technology to complex systems. He holds a masters degree in psychology with a specialization in human factors engineering and he is a Board Certified Human Factors Engineering Profesional

reduced manning is the process (and the result) of removing human functions from a system while retaining or improving system operability and effectiveness. reliability and maintainability characterize a system's operability and effectiveness. reduced manning impacts system reliability by changing the characteristics of (1) human error associated with system operation and maintenance, (2) time to repair failed components, and (3) mean-time-between-failures (MBTF) in a reduced manning environment. Simply reducing manning without compensating for system dependence on human involvement generally has a negative impact on system maintainability. Methods to address this include (1) human-system integration design of maintenance interfaces and (2) design of operations activities that are closely related to device failures. After demonstrating reliable performance through testing and operation, ship commanders can be assured that fewer people can effectively operate and maintain Navy ships and systems.

关键词： Naval vessels

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reliable 0.28 μm metal contact technology

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Journal of Vacuum Science & technology B: Microelectronics Processing and Phenomena 1997年第5期15卷 1775-1775页

作者： Kim, J.S. Kang, C.J. Park, J.W. Chung, S.H. Kim, B.C. Lee, J.Y. Park, J.W. R&D Center Technology Development Semiconductor Business Samsung Electronics Co. Kiheung-Eup Yongin-Gun Kyungki-Do Korea

A reliable small metal contact (MC) process is developed for the gigabit scaled dynamic random access memories (drAMs). The high aspect ratio contact etch was accomplished by using a high density inductively coupled plasma reactor. The low contact resistance of the MC for the gigabit scaled drAMs is realized when the amount of Si consumption at the bottom of the contact holes is minimized (<20 nm). The dopant activation of the source and drain (S/d) regions is also critical to have low contact and sheet resistances (rc and rs). Use of the high temperature (>950 °C) rapid thermal annealing enhances the dopant activation and effectively reduces the rc and rs. Surface treatment of the bottom of the contact hole after dry etch, becomes a key factor to have low contact resistance in the case of small contacts. The conventional Ar+ in situ sputter cleaning deteriorates the contact resistance of the vertically sloped small MCs. Light etch using CF4 and O2 gases removes damaged layer and improves contact resistance. rapid thermal nitridation after TiN barrier metal deposition also improves electrical properties of the MCs.

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