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A Unified Machine Learning Through Focus resist 3-d Structure Model

IEEE TrANSACTIONS ON SEMICONdUCTOr MANUFACTUrING 2024年第1期37卷 59-66页

作者： Xia, Mingyang Yan, Yan Li, Chen Shi, Xuelong Shanghai Integrated Circuits R&D Ctr Shanghai 201210 Peoples R China

To ensure post OPC data quality, examination based on estimated resist contours at resist bottom alone is insufficient, reliable prediction of lithography performance within process window must rely on complete information of on-wafer resist 3d structures. In this regard, resist 3d structure model, in particular, the through focus resist 3d structure model, with full chip capability will be the ultimate model in demand. To develop machine learning resist 3d structure models,we have proposed the physics-based information encoding scheme, together with carefully chosen deep convolution neural network and model training strategies. Our proposed through focus resist 3d structure model is based on conditional U-net structure with first five eigen images as model's main inputs and the focus setting as the conditional input. The average normalized cross correlation (NCC) or mean structure similarity index between ground truth and model predicted resist 3d structures can reach 0.92. With single GPU (Tesla M60), it takes 6.1ms for the model to produce resist 3d structure covering area of 1.8umx1.8 um . The model is fast enough and can be engineered for full chip implementation. The model can extend the capability of detecting lithography process window aware resist loss related hotspots.

关键词： resists Solid modeling Three-dimensional displays Lithography data models Semiconductor device modeling Computational modeling Through focus resist 3d structure model lithography hotspot detection physics based information encoding

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design and realization of Multi channel Programmable Power Supply SIP Based on FPGA 25

Design and Realization of Multi channel Programmable Power S...

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25th International Conference on Electronic Packaging Technology (ICEPT)

作者： Jiang, Shaozhuang Han, Guorong Yang, Yang Xue, Yang Jing, Qiang Shennan Circuits Co Ltd R&D Dept Shenzhen Peoples R China

ISBN: (纸本)9798350353808

Owing to its excellent parallel computing capabilities and distinctive on-site programmability, Field-Programmable Gate Array (FPGA) technology is deemed indispensable within specialized domains. Nonetheless, prevailing methodologies relying on discrete components to build power supply circuits for FPGA entail considerable drawbacks, including substantial footprint, elevated design expenditures, diminished stability, and pronounced electromagnetic interference, thereby circumscribing the breadth of FPGA utilization scenarios. This study endeavors to mitigate such constraints by devising a Power Management System-in-Package (SIP) featuring multiple independent and configurable power rails, tailored to the power exigencies of large-scale FPGA characterized by high core current demands and different power supply voltage levels for multiple BANKs. The proposed system integrates nine dC-dC units and one LdO unit to furnish autonomous power delivery to ten distinct power rails, each offering individually adjustable outputs. Programming control is realized through the utilization of compact logic devices for power enablement and millisecond-level timing management. The buried PCB technology is applied to encapsulate multiple active and passive devices into a single module measuring 22mmx22mmx7.4mm. Experimental evaluation of the module's VOUT1 reveals an approximate conversion efficiency of 89.2% under typical output conditions of 1V10A. When configured solely with 2x22uF ceramic capacitors and subjected to a substantial load of 20A, the observed output ripple remains <= 1.95%. The module boasts a maximum total output power of 125W and exhibits robust operational stability within an environmental range spanning from -55 degrees C to 85 degrees C, with a notable maximum shock resistance acceleration exceeding >= 5000g. The embedded power module implemented in this study features multiple power rails, robust environmental stability, and rapid deployment capabilities, thereby

关键词： power supply module programmable multiple power rails rapid deployment

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Plasmon-enhanced absorption in dielectric layer coated III-V nanowire array decorated with nanoparticles

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OPTICAL MATErIALS 2025年 162卷

作者： Zhu, Hanchen Chu, Yanmeng Shang, Fuxiang Zhang, Linjun Chen, Yunqi Wang, Haodong Chen, Zhouxiang Hou, Qichao Chen, Lulu Qin, Weiou Cheng, Zhiyuan Zhang, Yunyan Zhejiang Univ Coll Integrated Circuits Hangzhou 311200 Zhejiang Peoples R China Zhejiang CMOS Integrated Circuit Complete Proc & D Hangzhou 311200 Peoples R China

The group III-V nanowires (NWs) have broad prospects in the field of photoelectric detection, among which GaN and InN NWs are promising candidates for ultraviolet (UV) and short-wave infrared (SWIr) photodetectors but have rarely been studied in depth. Furthermore, there is a lack of research on the further improvement of their photoelectric performance. In this research, we introduce a thin dielectric layer in the structure of nanowire array decorated with metal nanoparticles (NPs) for the first time, demonstrating how dielectric layer between NWs and NPs further improve light absorption efficiency. Surface plasmons (SPs) excited by NPs, along with the dielectric layer which can concentrate the incident light, result in obvious enhancement of the absorption rate, the rationality of this design is supported by the calculation results in both ultraviolet UV and SWIr range. For GaN NWs, light absorption rate can be increased from 76 % to 96 % near 335 nm and for InN NWs the peak of absorption curve rises from 49 % to 97 % near 1550 nm. The simulation results will provide a reference for improving the performance of photodetectors.

关键词： Surface plasmon III-V semiconductor GaN/InN nanowire COMSOL multiphysics UV/SWIr photodetector

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New structure transistors for advanced technology node CMOS ICs

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National Science review 2024年第3期11卷 24-41页

作者： Qingzhu Zhang Yongkui Zhang Yanna Luo Huaxiang Yin Integrated Circuit Advanced Process R&D Center Institute of Microelectronics of Chinese Academy of Sciences(IMECAS) State key Lab of Fabrication Technologies for Integrated Circuits Institute of Microelectronics of Chinese Academy of Sciences School of Integrated Circuits University of Chinese Academy of Sciences

Over recent decades, advancements in complementary metal-oxide-semiconductor integrated circuits(ICs)have mainly relied on structural innovations in transistors. From planar transistors to the fin field-effect transistor(FinFET) and gate-all-around FET(GAAFET), more gate electrodes have been added to three-dimensional(3d) channels with enhanced control and carrier conductance to provide higher electrostatic integrity and higher operating currents within the same device footprint. Beyond the 1-nm node, Moore's law scaling is no longer expected to be applicable to geometrical shrinkage. Vertical transistor stacking, e.g. in complementary FETs(CFET), 3d stack(3dS) FETs and vertical-channel transistors(VFET), for enhanced density and variable circuit or system design represents a revolutionary scaling approach for sustained IC development. Herein, innovative works on specific structures, key process breakthroughs, shrinking cell sizes and design methodologies for transistor structure research and development are reviewed. Perspectives on future innovations in advanced transistors with new channel materials and operating theories are also discussed.

关键词： transistor CMOS GAAFET CFET 3dS FET

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recess-free enhancement-mode AlGaN/GaN rF HEMTs on Si substrate

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Journal of Semiconductors 2024年第6期45卷 81-86页

作者： Tiantian Luan Sen Huang Guanjun Jing Jie Fan Haibo Yin Xinguo Gao Sheng Zhang Ke Wei Yankui Li Qimeng Jiang Xinhua Wang Bin Hou Ling Yang Xiaohua Ma Xinyu Liu High-Frequency High-Voltage Device and Integrated Circuits R&D Center Institute of Microelectronics of Chinese Academy of SciencesBe i-jing 100029China School of integrated Circuits University of Chinese Academy of SciencesBeijing 100049China Faculty of integrated Circuits Xidian UniversityXi’an 710071China

Enhancement-mode(E-mode)GaN-on-Si radio-frequency(rF)high-electron-mobility transistors(HEMTs)were fabri-cated on an ultrathin-barrier(UTB)AlGaN(<6 nm)/GaN heterostructure featuring a naturally depleted 2-d electron gas(2dEG)*** fabricated E-mode HEMTs exhibit a relatively high threshold voltage(VTH)of+1.1 V with good uniformity.A maxi-mum current/power gain cut-off frequency(fT/fMAX)of 31.3/99.6 GHz with a power added efficiency(PAE)of 52.47%and an out-put power density(Pout)of 1.0 W/mm at 3.5 GHz were achieved on the fabricated E-mode HEMTs with 1-μm gate and Au-free ohmic contact.

关键词： AlGaN/GaN heterostructure ultrathin-barrier enhancement-mode radio-frequency power added efficiency silicon substrate

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Can optical proximity correction solution be learned? The learning limit and a general learning framework

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JOUrNAL OF MICrO-NANOPATTErNING MATErIALS ANd METrOLOGY-JM3 2022年第4期21卷

作者： Shi, Xuelong Yan, Yan Li, Chen Xia, Mingyang Pan, Bingyang Gao, Ying Yuan, Wei Shanghai Integrated Circuits R&D Ctr Shanghai Peoples R China

Background: Optical proximity correction (OPC) is an indispensable technology that has been propelling the advancement of computational lithography technology. To tightly control edge placement error (EPE) and maintain lithography process window, the demands on OPC computational resources and OPC turnaround time are growing rapidly with alarming acceleration. To tame the trend, machine learning technologies have been explored;however, an in-depth discussion on OPC solution learning limit is still ***: We aim to present an in-depth discussion on OPC solution learning limit and propose a general machine learning OPC framework that can be extended to curvilinear mask OPC ***: In this study, we first investigate the machine learning OPC learning limit by examining noninverse lithography technology (non-ILT) OPC solution space characteristics inherited from edge segmentation and control point setting rules and then propose a general machine learning OPC framework that can take full advantage of deep convolution neural network (dCNN) learning capability while being able to preserve mask data high ***: With this machine learning OPC framework, we have achieved models with average absolute model error < 1 nm for 14-nm metal layer. With single GPU, the average time for machine learning OPC models to produce results of 3840 nm x 3840 nm area is 8.74 ms for single channel input model and 12.65 ms for six channels input ***: For non-ILT OPC solution, there is an intrinsic learning limit inherited from edge segmentation rules. Machine learning OPC models should be content with learning low order OPC solutions. This intrinsic learning limit of non-ILT OPC solution may diminish for ILT OPC solution when the constraint on degrees of freedom of OPC solution is lifted. The machine learning OPC framework we proposed is general and extendable to curvilinear OPC technology. (c) 2022 Society of Photo-Optical Instrumentation Engineers (

关键词： optical proximity correction solution learning limit machine learning optical proximity correction curvilinear mask optical proximity correction

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rIS assisted wireless networks: Collaborative regulation, deployment mode and field testing

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IET COMMUNICATIONS 2024年第20期18卷 1665-1682页

作者： Zhao, Yajun Beijing Inst Technol Sch Integrated Circuits & Elect Beijing 100081 Peoples R China ZTE Corp Wireless & Comp Product R&D Inst Beijing Peoples R China

In recent years, reconfigurable intelligent surfaces (rIS) have made significant progress in engineering application research and industrialization, as well as in academic research. However, the engineering application research field of rIS still faces several challenges. This article analyses and discusses the two deployment modes of rIS-assisted wireless networks, namely network controlled mode and standalone mode. It also presents three typical collaboration scenarios of rIS networks, including multi-rIS collaboration, multi-user access, and multi-cell coordination, which reflect the differences between the two deployment modes of rIS. The article proposes collaborative regulation mechanisms for rIS and analyses their applications in the two network deployment modes in-depth. Furthermore, the article establishes simulation models of three scenarios and provides rich numerical simulation results. An actual field test environment is also built, where a specially designed and processed rIS prototype was used for preliminary field test and verification. Finally, this article puts forward future trends and challenges.

关键词： 5G 6G collaborative regulation deployment mode radio access networks reconfigurable intelligent surfaces

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Hybrid Integration of Gate-All-Around Stacked Si Nanosheet FET and Si/SiGe Super-Lattice FinFET to Optimize 6T-SrAM for N3 Node and Beyond

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IEEE TrANSACTIONS ON ELECTrON dEVICES 2024年第3期71卷 1776-1783页

作者： Zhang, Xuexiang Yao, Jiaxin Luo, Yanna Cao, Lei Zheng, Yantong Zhang, Qingzhu Wu, Zhenhua Yin, Huaxiang Chinese Acad Sci Inst Microelect Integrated Circuit Adv Proc R&D Ctr Beijing 100029 Peoples R China Chinese Acad Sci State Key Lab Fabricat Technol Integrated Circuits Beijing 100029 Peoples R China Univ Chinese Acad Sci Sch Integrated Circuits Beijing 100049 Peoples R China

The implementation of vertically stacked gate-all-around nanosheet FET (GAA NSFET) may help improve the performance of static random access memory (SrAM) for the design flexibility with variable NS widths. However, the method that often relies on the increasing of device width for higher driving current is to cause an increased SrAM cell area and degrade the scalability of transistor in advanced nodes. In this article, an innovated SrAM bitcell design with hybrid integration of Si NSFET and Si/SiGe super-lattice FinFET (SL-FinFET) in one SrAM cell is proposed for less area and improved performance in 3 nm and beyond nodes. Under the same footprint, p-type SL-FinFET delivers obviously enhanced driving current compared with NSFET and it may yield improved circuit performance for the SrAM cell with natural transistor ratio. The integration process method and the layout schemes for two kinds of typical 6T-SrAM cells, including the high-robustness cell (HI-r Cell) and the high-speed cell (HI-S Cell) with the hybrid integration method, are presented for optimizing high-density (Hd) and high-performance (HP) SrAM. As compared with the Hd NSFET SrAM cell, the Hd HI-r Cell achieves 16.2% improvement in read static noise margin (rSNM) and the Hd HI-S Cell achieves 21.6% reduction in read time and 28.6% reduction in write time. The HP hybrid integrated cell even pushes the SrAM cell performance arriving to the theoretical limits of regular NSFETs. Moreover, the hybrid integration scheme may provide another revolutionary method to optimize transistor ratio by adjusting the height of SiGe thickness in the transistors.

关键词： 3-nm process node 6T static random access memory (6T-SrAM) hybrid integration Si/SiGe super-lattice FinFET (SL-FinFET) vertically stacked gate-all-around nanosheet FET (GAA NSFET)

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Fully integrated multi-mode optoelectronic memristor array for diversified in-sensor computing

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NATUrE NANOTECHNOLOGY 2025年第1期20卷 1-11页

作者： Huang, Heyi Liang, Xiangpeng Wang, Yuyan Tang, Jianshi Li, Yuankun du, Yiwei Sun, Wen Zhang, Jianing Yao, Peng Mou, Xing Xu, Feng Zhang, Jinzhi Lu, Yuyao Liu, Zhengwu Wang, Jianlin Jiang, Zhixing Hu, ruofei Wang, Ze Zhang, Qingtian Gao, Bin Bai, Xuedong Fang, Lu dai, Qionghai Yin, Huaxiang Qian, He Wu, Huaqiang Tsinghua Univ Beijing Innovat Ctr Integrated Circuits Sch Integrated Circuits Beijing Peoples R China Tsinghua Univ Beijing Natl Res Ctr Informat Sci & Technol Beijing Peoples R China Chinese Acad Sci Integrated Circuit Adv Proc R&D Ctr Inst Microelect State Key Lab Fabricat Technol Integrated Circuits Beijing Peoples R China Chinese Acad Sci Inst Microelect Key Lab Fabricat Technol Integrated Circuits Beijing Peoples R China Tsinghua Univ Dept Elect Engn Beijing Peoples R China Chinese Acad Sci Inst Phys Beijing Natl Lab Condensed Matter Phys Beijing Peoples R China

In-sensor computing, which integrates sensing, memory and processing functions, has shown substantial potential in artificial vision systems. However, large-scale monolithic integration of in-sensor computing based on emerging devices with complementary metal-oxide-semiconductor (CMOS) circuits remains challenging, lacking functional demonstrations at the hardware level. Here we report a fully integrated 1-kb array with 128 x 8 one-transistor one-optoelectronic memristor (OEM) cells and silicon CMOS circuits, which features configurable multi-mode functionality encompassing three different modes of electronic memristor, dynamic OEM and non-volatile OEM (NV-OEM). These modes are configured by modulating the charge density within the oxygen vacancies via synergistic optical and electrical operations, as confirmed by differential phase-contrast scanning transmission electron microscopy. Using this OEM system, three visual processing tasks are demonstrated: image sensory pre-processing with a recognition accuracy enhanced from 85.7% to 96.1% by the NV-OEM mode, more advanced object tracking with 96.1% accuracy using both dynamic OEM and NV-OEM modes and human motion recognition with a fully OEM-based in-sensor reservoir computing system achieving 91.2% accuracy. A system-level benchmark further shows that it consumes over 20 times less energy than graphics processing units. By monolithically integrating the multi-functional OEMs with Si CMOS, this work provides a cost-effective platform for diverse in-sensor computing applications. This study reports a fully integrated 128 x 8 optoelectronic memristor array with Si complementary metal-oxide-semiconductor circuits, featuring configurable multi-mode functionality. It demonstrates diversified in-sensor computing tasks and consumes 20 times less energy than GPUs.

关键词： CMOS integrated circuits

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demonstration of Efficient Non-Volatile Boolean Logic With Non-Volatile and Ambipolar Fin Field-Effect Transistors for In-Memory Computing

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ELECTrONICS LETTErS 2025年第1期61卷

作者： Liu, Siyuan Zhang, Zhaohao Zhong, Kun Xu, Gaobo Zhang, Qingzhu Li, Junfeng Yin, Huaxiang Chinese Acad Sci Integrated Circuit Adv Proc R&D Ctr Inst Microelect Beijing Peoples R China Chinese Acad Sci Inst Microelect State Key Lab Fabricat Technol Integrated Circuits Beijing Peoples R China Univ Chinese Acad Sci Chinese Acad Sci Sch Integrated Circuits Beijing Peoples R China

In this letter, we demonstrate an efficient non-volatile Boolean logic based on a single Schottky barrier and ferroelectric FinFET (SB-Fe FinFETs) has been proposed and experimentally demonstrated. Ferroelectric HZO and metallic source and drain (MSd) were adopted r for non-volatile and ambipolar characteristics on the devices. Benefiting from the designed multi-level reading operation and the non-volatile ambipolar characteristics, complete Boolean logic functions have been demonstrated on single SB-Fe FinFET. Furthermore, thanks to the single gate pulse for both input B and read operation, all Boolean logic functions can be implemented in two steps. robust output current and high speed for the logic functions are identified in the experimental results, indicating the technology promising for future logic-in-memory applications.

关键词： bipolar transistors ferroelectric devices ferroelectric storage

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