We investigate basic communication protocols in ad-hoc mobile networks. We follow the semi-compulsory approach according to which a small part of the mobile users, the support Σ, that moves in a predetermined way is ...
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The problem of determining the unsatisfiability threshold for random 3-SAT formulas consists in determining the clause to variable ratio that marks the experimentally observed abrupt change from almost surely satisfia...
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The problem of determining the unsatisfiability threshold for random 3-SAT formulas consists in determining the clause to variable ratio that marks the experimentally observed abrupt change from almost surely satisfiable formulas to almost surely unsatisfiable. Up to now, there have been rigorously established increasingly better lower and upper bounds to the actual threshold value. In this paper, we consider the problem of bounding the threshold value from above using methods that, we believe, are of interest on their own right. More specifically, we show how the method of local maximum satisfying truth assignments can be combined with results for the occupancy problem in random allocation schemes of balls into bins in order to achieve an upper bound for the unsatisfiability threshold less than 4.571. Thus we improve over the best, with an available complete proof, previous upper bound, which was 4.596. In order to obtain this value, we also establish a bound on the q-binomial coefficients (a generalization of the binomial coefficients) which, we believe, is of independent interest.
In this paper, we propose a novel algorithm based on evolutionary computation techniques to extract an optimal user profile. This method originates from the simulation of the human immune system for finding binary str...
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This paper proposes a clustering method for nominal and numerical data based on Rough Sets and its application to knowledge discovery in the medical database. Classification is performed according to the indiscernibil...
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The continued growth of microprocessors' performance and the need for better CPU utilization, has led to the introduction of the software peripherals' approach: By this term we refer to software modules that c...
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ISBN:
(纸本)1581133642
The continued growth of microprocessors' performance and the need for better CPU utilization, has led to the introduction of the software peripherals' approach: By this term we refer to software modules that can successfully emulate peripherals that, until now, were traditionally implemented in hardware. Software implementations offer great flexibility in product design and in functional upgrades, while they have high contribution in the cost/performance ratio optimization. We focus on embedded applications, where the cost and the short time to market are the leading issues. In this paper, we study the hardware and software requirements for developing a generic microprocessor with support for software peripherals. Additionally, we present three software peripherals, a Universal Asynchronous Receiver Transmitter, a keypad controller and a dot matrix LCD controller, and we analyze their impact in CPU occupation. Finally, we explore the impact of using a software UART on system power dissipation.
The data paths of most contemporary general and special purpose processors include registers, adders and other arithmetic circuits. If these circuits are also used for built-in self-test, the extra area required for e...
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ISBN:
(纸本)0769510256
The data paths of most contemporary general and special purpose processors include registers, adders and other arithmetic circuits. If these circuits are also used for built-in self-test, the extra area required for embedding testing structures can be cut down efficiently. Several schemes based on accumulators, subtracters, multipliers and shift, resisters have been proposed and analyzed in the past for parallel test response compaction, whereas some efforts have also been devoted in the bit-serial response compaction case. In this paper, we analyse and evaluate the bit-serial version of a recently proposed scheme for parallel test response compaction. Experimental results on the ISCAS'85 benchmark circuits indicate that the post-compaction fault coverage drop attained by the new scheme is significantly lower than other already known accumulator-based compaction schemes.
Presents a WWW-based tool for the generation of arithmetic soft cores for a wide variety of functions, operand sizes and architectures. The tool produces structural and synthesizable VHDL and/or Verilog descriptions a...
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ISBN:
(纸本)0769512062
Presents a WWW-based tool for the generation of arithmetic soft cores for a wide variety of functions, operand sizes and architectures. The tool produces structural and synthesizable VHDL and/or Verilog descriptions and covers several arithmetic operations, such as addition, subtraction, multiplication, division, squaring, square rooting and shifting. Therefore, designs requiring arithmetic cores, as for example those in digital signal processing and multimedia applications, can be completed faster and with less effort.
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