It is known that for the adaptive filtering problem, the Multi Model Adaptive Filter (MMAF) based to the Partitioning Theorem is the best solution. It is also known that Genetic Algorithms (GAs) are one of the best me...
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It is known that for the adaptive filtering problem, the Multi Model Adaptive Filter (MMAF) based to the Partitioning Theorem is the best solution. It is also known that Genetic Algorithms (GAs) are one of the best methods for searching and optimization. In this work a new method, concerning multivariable systems, which combines the effectiveness of MMAF and GAs' robustness has been developed. Specifically, the a-posteriori probability that a specific model, of the bank of the conditional models, is the true model can be used as fitness function for the G A. Although the parameters' coding is more complicated, simulation results show that the proposed algorithm succeeds better estimation of the unknown parameters compared to the conventional MMAF, even in the case where it is not included in the filters bank. Finally, a variety of defined crossover and mutation operators is investigated in order to accelerate algorithm's convergence.
This paper presents a novel method for designing type-I and type-II single and double output TSC Berger code checkers taking into account a realistic fault model including stuck-at, transistor stuck-open, transistor s...
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This paper presents a novel method for designing type-I and type-II single and double output TSC Berger code checkers taking into account a realistic fault model including stuck-at, transistor stuck-open, transistor stuck-on, resistive bridging faults and breaks. A benefit of the proposed type-I single and double output checkers is that all faults are testable by a very small set of code words the number of which does not increase with the information length, that is, the checkers are C-testable. The proposed double output checkers are two-times faster than the corresponding single output checkers, but require for their implementation twice as many transistors as the single output checkers. The proposed single output checkers are the first known TSC Berger code checkers in the open literature, while the type-I single output checkers are near optimal with respect to the number of the transistors required for their implementation. The checkers of this paper with either, single or double output are significantly more efficient, with respect to the implementation area and speed than the already known from the open literature Berger code checkers.
The ability to exchange in a meaningful secure and simple fashion relevant healthcare data about patients is seen as vital in the context of efficient and cost-effective shared or team-based care. The electronic healt...
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Instruction caches are usually designed to fetch the whole block from memory in case of a miss. However, the fetched blocks might contain branch instructions which if taken, will render the rest of the block useless. ...
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Instruction caches are usually designed to fetch the whole block from memory in case of a miss. However, the fetched blocks might contain branch instructions which if taken, will render the rest of the block useless. A novel approach is introduced, namely the Precise Control, which fetches only the words of a cache block that are likely to be used. The performance of Precise Control is evaluated and it is shown that it has a positive influence on system performance. Precise Control reduces the words fetched from memory by up to 60%, thus reducing significantly the communication overhead between cache and main memory as well as the total execution time.
Presents the architecture of a system for the rapid prototyping of digital circuits that is based an the Altera FLEX8000 reconfigurable set of FPGAs. The interconnection architecture of the system consists of both fix...
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Presents the architecture of a system for the rapid prototyping of digital circuits that is based an the Altera FLEX8000 reconfigurable set of FPGAs. The interconnection architecture of the system consists of both fixed lines between adjacent FPGAs and shared lines that are capable of interconnecting more than two devices. The reconfigurable set of devices is placed on a 2D grid. The external interface of the system enables the connection of two or more base modules to construct a larger grid with similar characteristics.
A new method for estimating 3D motion parameters from point correspondences is presented in this paper. The problem formulation leads to the solution of an overdetermined linear system of equations. The total least sq...
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A new method for estimating 3D motion parameters from point correspondences is presented in this paper. The problem formulation leads to the solution of an overdetermined linear system of equations. The total least squares (TLS) method is found to be the most suitable one for estimating the solution since our model includes noise both in the observation data and in the system matrix. The translation parameters are obtained immediately from the above solution whereas the rotation parameters are estimated from the solution of another TLS problem. Tests of our method on artificial data and on real images show its robustness against Gaussian additive noise and against digitalization noise introduced by finite pixel resolution.
This paper reports on a workshop on Problem Formulation in Multi-Criteria Decision Analysis held at SPUDM97. The focus of the workshop was the problem formulation phase which occurs between the analyst meeting a perso...
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