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16th International Conference on ENTERprise Information systems, CENTERIS 2024 - 12th International Conference on Project MANagement, ProjMAN 2024 - 14th International Conference on Health and Social Care Information systems and Technologies, HCist 2024

作者： Freitas, Alberto Costa, Bruno Martinho, Diogo Pais, Fatima Duarte, Ivone Martins, Constantino Marreiros, Goreti Almeida, Rute MEDCIDS Faculty of Medicine University of Porto Porto4200-450 Portugal CINTESIS at RISE University of Porto Porto4200-450 Portugal GECAD-Res. Group on Intelligent Engineering and Computing for Advanced Innovation and Development Institute of Engineering-Polytechnic of Porto LASI-Intelligent Systems Associate Laboratory Guimarães 4249-015 Porto4800-058 Portugal Sucessos Criativos Lda São João da Madeira 3700-121 Portugal Centro Hospitalar Universitário São João Porto4200-319 Portugal

The project WAI aims to tackle the growth of mental health disorders among the younger population, namely the most prevalent anxiety disorders. It intends to enhance educational strategies to help schools, teachers, and other professionals dealing with student anxiety. With that purpose, a suite of resources with a focus on mental health promotion in the school environment was organized by collecting existing tools and creating new elements for completeness. Information on mental health, AI, and AI use on mental health, classroom strategies, and best practices, structured for interdisciplinary application and use by both teachers and students, were considered. These resources were integrated into a Toolkit with a recommendation feature, which allows easy location and access to the most adequate tool for the specific need or educational challenge. To maximize accessibility, resources will be translated into several languages. The Toolkit will guide the implementation of a capacitation formative program for educators that will be implemented based on its resources. The development of the project involves participatory design with contributions from educators, mental health experts, and AI technologists to ensure a comprehensive approach. The Toolkit is intended to provide a systematic framework for educators to promote sustainable mental health promotion practices and, when appropriate, to use AI in ways that are ethically sound, while fostering digital responsibility. © 2025 The Author(s).

关键词： Students

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A multidisciplinary approach to prevent student anxiety: a Toolkit for educators

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Procedia Computer Science 2025年 256卷 852-860页

作者： Alberto Freitas Bruno Costa Diogo Martinho Fatima Pais Ivone Duarte Constantino Martins Goreti Marreiros Rute Almeida MEDCIDS Faculty of Medicine University of Porto Porto 4200-450 Portugal CINTESIS@RISE University of Porto Porto 4200-450 Portugal Centro Hospitalar Universitário São João 4200-319 Porto GECAD – Research Group on Intelligent Engineering and Computing for Advanced Innovation and Development Institute of Engineering – Polytechnic of Porto Porto 4249-015 Portugal & LASI – Intelligent Systems Associate Laboratory Guimarães 4800-058 Portugal Sucessos Criativos Lda São João da Madeira 3700-121 Portugal

关键词： Mental Health Promotion Anxiety Disorders Educational Strategies AI in Education Toolkit Teacher Capacitation

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Reconstructing hardware transactional memory for workload optimized systems 1

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Lecture Notes in Computer Science

作者： Korgaonkar, Kunal Jain, Prabhat Tomar, Deepak Garimella, Kashyap Kamakoti, Veezhinathan RISE - Reconfigurable and Intelligent Systems Engineering Group Indian Institute of Technology Madras Chennai India

ISBN: (数字)9783642241512

ISBN: (纸本)9783642241505

Workload optimized systems consisting of large number of general and special purpose cores, and with a support for shared memory programming, are slowly becoming prevalent. One of the major impediments for effective parallel programming on these systems is lock-based synchronization. An alternate synchronization solution called Transactional Memory (TM) is currently being explored. We observe that most of the TM design proposals in literature are catered to match the constrains of general purpose computing platforms. Given the fact that workload optimized systems utilize wider hardware design spaces and on-chip parallelism, we argue that Hardware Transactional Memory (HTM) can be a suitable implementation choice for these systems. We re-evaluate the criteria to be satisfied by a HTM and identify possible scope for relaxations in the context of workload optimized systems. Based on the relaxed criteria, we demonstrate the scope for building HTM design variants, such that, each variant caters to a specific workload requirement. We carry out suitable experiments to bring about the trade-off between the design variants. Overall, we show how the knowledge about the workload is extremely useful to make appropriate design choices in the workload optimized HTM. © 2011 Springer-Verlag.

关键词： Parallel programming

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Efficient grouping of Fail Chips for Volume Yield Diagnostics

Efficient Grouping of Fail Chips for Volume Yield Diagnostic...

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International Conference on VLSI Design

作者： Lavanya Jagan Ratan Deep Singh V. Kamakoti Ananta K. Majhi Reconfigurable & Intelligent Systems Engineering Group Department of Computer Science and Engineering Indian Institute of Technology Chennai India NXP Semiconductors Corporate Innovation and Technology Research Eindhoven Netherlands

Volume Yield Diagnostics (VYD) is crucial to diagnose critical systematic yield issues from the reports obtained by testing thousands of chips. This paper presents an efficient clustering technique for VYD that has be... 详细信息

关键词： Runtime Design engineering Electronics industry Inspection Very large scale integration intelligent systems systems engineering and theory Computer science Technological innovation Semiconductor device testing

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Programmable architectures for large-scale implementations of Spiking Neural Networks

Programmable architectures for large-scale implementations o...

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IET Irish Signals and systems Conference (ISSC 2008)

作者： Jim Harkin Liam McDaid Steve Hall Thomas Dowrick Fearghal Morgan Intelligent Systems Research Centre University of Ulster Ireland Department of Electrical Engineering & Electronics University of Liverpool UK Bio-Inspired Electronics & Reconfigurable Computing Group NUI Galway Ireland

ISBN: (纸本)9780863419317

FPGA devices have emerged as a popular platform for the rapid prototyping of biological Spiking Neural Network (SNNs) applications, offering the key requirement of reconfigurability. However, FPGAs do not efficiently realise the biologically plausible neuron and synaptic models of SNNs, and current FPGA routing structures cannot accommodate the high levels of inter-neuron connectivity inherent in complex SNNs. This paper highlights and discusses the current challenges of implementing large scale SNNs on reconfigurable FPGAs. The paper proposes a novel, large scale Field Programmable Neural Network (FPNN) architecture, incorporating low power analogue synapses and SNN neurons, interconnected using a Network on Chip architecture for SNN spike packet routing and SNN configuration. Initial results on the scalability of the proposed FPNN architecture are presented.

关键词： Network-on-Chip Spiking Neural Networks Programmable Hardware FPNN

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reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks

Reconfigurable platforms and the challenges for large-scale ...

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International Conference on Field Programmable Logic and Applications

作者： Jim Harkin Fearghal Morgan Steve Hall Piotr Dudek Thomas Dowrick Liam McDaid Bio-Inspired Electronics Reconfigurable Computing Group NUI Galway Ireland Intelligent Systems Research Centre University of Ulster UK Institute for Nanoscale Science Engineering & Technology University of Liverpool UK School of Electrical and Electronic Engineering University of Manchester Institute of Science and Technology UK

FPGA devices have witnessed popularity in their use for the rapid prototyping of biological Spiking Neural Network (SNNs) applications, as they offer the key requirement of reconfigurability. However, FPGAs do not efficiently realise the biological neuron/synaptic models. Also their routing structures cannot accommodate the high levels of neuron inter-connectivity inherent in complex SNNs. This paper highlights and discusses the current challenges of implementing large scale SNNs on reconfigurable FPGAs. The paper presents a novel Field Programmable Neural Network (FPNN) architecture incorporating low power analogue synapse and a network on chip architecture for SNN routing and configuration. Initial results are presented.

关键词： Neurons Tiles Computer architecture Field programmable gate arrays Biology Hardware Integrated circuit interconnections

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A genetic approach to gateless custom VLSI design flow

A genetic approach to gateless custom VLSI design flow

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19th International Conference on Microelectronics, ICM

作者： Shoaib, Mohammed Noor Mahammad, Sk. Kamakoti, V. Reconfigurable and Intelligent Systems Engineering Group Department of Computer Science and Engineering Indian Institute of Technology Madras Chennai - 600036 India

ISBN: (纸本)9781424418473

In this work, we propose a novel technique for evolving transistor netlists from truth table descriptions of arbitrary digital circuits. The proposed methods incorporate the effective use of Genetic Algorithms (GAs). In typical semi-custom and custom design flows, logic optimization is done at the gate level after Boolean translation of the input truth table. The final transistor netlist is then deduced from the simplified gate logic to be laid out on a chip. However transistor level optimizations after the boolean simplification step would still not lead to the minimum number of transistors. This final optimization level is non-existent in present custom design flows. This work aims to address this need. A salient feature of the proposed technique is the bypassing of gate level representation and optimization in the VLSI design flow. We provide genetic methods to directly optimize truth table inputs using transistor level simplification. This eliminates the intermediate gate level optimization step and provides optimized transistor netlists which could be used for dynamic library cell generation for custom and semi-custom designs on the fly. © 2007 IEEE.

关键词： Transistors

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Efficient building blocks for reversible sequential circuit design

Efficient building blocks for reversible sequential circuit ...

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2006 49th Midwest Symposium on Circuits and systems, MWSCAS'06

作者： Hari, Siva Kumar Sastry Shroff, Shyam Mahammad, Sk. Noor Mahammad Kamakoti, V. Reconfigurable and Intelligent Systems Engineering Group Department of Computer Science and Engineering Indian Institute of Technology Madras Chennai - 600 036 India

ISBN: (纸本)1424401739

Reversible logic is gaining Interest in the recent past due to its less heat dissipating characteristics. It has been proved that any Boolean function can be implemented using reversible gates. In this paper we propose a set of basic sequential elements that could be used for building large reversible sequential circuits leading to logic and garbage reduction by a factor of 2 to 6 when compared to existing reversible designs reported In the literature. © 2006 IEEE.

关键词： Sequential circuits

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Efficient Building Blocks for Reversible Sequential Circuit Design

Efficient Building Blocks for Reversible Sequential Circuit ...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： Siva Kumar Sastry Hari Shyam Shroff Sk. Noor Mahammad V. Kamakoti Reconfigurable and Intelligent Systems Engineering Group Indian Institute of Technology Madras Chennai India

Reversible logic is gaining interest in the recent past due to its less heat dissipating characteristics. It has been proved that any Boolean function can be implemented using reversible gates. In this paper we propose a set of basic sequential elements that could be used for building large reversible sequential circuits leading to logic and garbage reduction by a factor of 2 to 6 when compared to existing reversible designs reported in the literature.

关键词： Sequential circuits Logic circuits Boolean functions Energy dissipation Circuit synthesis Design engineering Logic design Logic gates intelligent systems intelligent structures

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