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Fault-Tolerance in real-time Systems

IFAC Proceedings Volumes 1991年第2期24卷 119-121页

作者： K.G. Shin G. Koob F. Jahanian Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science The University of Michigan Ann Arbor MI 48109-2122 USA Office of Naval Research Code 1133 800 N. Quincy Street Arlington VA 22217-5000 USA IBM T.J. Watson Research Center P.O. Box 704 Yorktown Heights NY 10598 USA

With ever-increasing reliance on digital computers in embedded systems such as in space, avionics, manufacturing, and life-support monitoring/control applications, the need for dependable systems that deliver services in a timely manner has become crucial. Embedded systems often interact with the external environment and operate under strict timeliness and reliability requirements. Fault tolerance and real-time requirements on a system often influence one another in subtle ways, for example, the requirements on a highly—available system, such as an air traffic control system, may derive the timing constraints imposed on certain critical tasks. In cases where a set of interacting tasks operate under strict timing constraints, missing a deadline may result in a catastrophic system failure, which was termed a dynamic failure in (Shin, Krishna, and Lee, 1985). This paper argues that fault- tolerance and real-time requirements are not orthogonal and it addresses some of the challenges that confront the designers of fault-tolerant real-time systems. These challenges include formal specification of reliability and timing requirements, appropriate language and operating system support for providing fault-tolerance in a time-critical system, new scheduling theories which consider multiple resources and fault-tolerance, tradeoff between time and space redundancy, and predictable redundancy management in the presence of faults.

关键词： Fault-tolerance real-time systems reliability time and space redundancy run-time monitoring specification

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A parallel algorithm for logic simulation on transputer networks

A parallel algorithm for logic simulation on transputer netw...

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Great Lakes Symposium on VLSI

作者： S. Srinivas A. Basu A. Paulraj L.M. Patnaik Department of Electrical and Computer Engineering Concordia University Montreal QUE Canada Centre for Development of Advanced Computing Bangalore India Microprocessor Applications Laboratory Supercomputing Education and Research Center Department of Computer Science and Automation Indian Institute of Science Bangalore India

The authors present a parallel algorithm for logic simulation of VLSI circuits. It is implemented on a network of transputers connected in a ring topology. The approach is based on partitioning a functionality matrix representation of the circuit among the transputers and adopting a data flow technique for the solution. A significant aspect of the algorithm is that it overlaps computation with communication, thereby reducing the communication overhead. It also attempts even distribution of load in order to reduce processor idle time. The algorithm possesses the advantages of ease of implementation and ease of extension to incorporate additional parameters for simulation. Performance results of the algorithm are given.< >

关键词： Parallel algorithms Circuit simulation Computational modeling Concurrent computing Application software Logic circuits Very large scale integration Algorithm design and analysis Logic design Design automation

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Intraventricular electrogram analysis for discrimination of ventricular tachycardia from ventricular fibrillation

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Journal of Electrocardiology 1991年 24卷 135-135页

作者： DiCarlo, Lorenzo A. Jenkins, Janice M. Kriegler, Catherine Medical Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan School of Medicine United States Cardiac Electrophysiology Laboratory St. Joseph Mercy Hospital Ann Arbor Michigan United States

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FULL-WAVE SOLUTION OF DIELECTRIC LOADED WAVE-GUIDES AND SHIELDED MICROSTRIPS UTILIZING FINITE-DIFFERENCE AND THE CONJUGATE-GRADIENT METHOD

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INTERNATIONAL JOURNAL OF MICROWAVE AND MILLIMETER-WAVE computer-AIDED engineering 1991年第4期1卷 346-357页

作者： NARAYANAN, V MANELA, M LADE, RK SARKAR, TK Department of Electrical and Computer Engineering Syracuse University Syracuse New York 13244-1240 Viswanathan Narayanan was born in Bangalore India on December 14 1965. He received the BE degree in Electronics and Communications from B.M.S. College of Engineering Bangalore in 1988. He joined the Department of Electrical Engineering at Syracuse University for his graduate studies in 1989 where he is currently a research assistant. His research interests are in microwave measurements numerical electromagnetics and signal processing. Biographies and photos are not available for M. Manela and R. K. Lade. Tapan K. Sarkar (Sf69-M'76-SM'X1) was born in Calcutta. India on August 2 1948. He received the BTech degree from the Indian Institute of Technology Kharagpur India in 1969 the MScE degree from the University of New Brunswick Fredericton Canada in 1971. and the MS and PhD degrees from Syracuse University. Syracuse NY in 1975. From 1975-1976 he was with the TACO Division of the General Instruments Corporation. He was with the Rochester Institute of Technology (Rochester NY) from 1976-1985. He was a Research Fellow at the Gordon Mckay Laboratory Harvard University Cambridge MA from 1977 to 1978. He is now a Professor in the Department of Electrical and Computer Engineering Syracuse University. His current research interests deal with numerical solutions of operator equations arising in electromagnetics and signal processing with application to system design. He obtained one of the “ best solution” awards in May 1977 at the Rome Air Development Center (RADC) Spectral Estimation Workshop. He has authored or coauthored more than 154 journal articles and conference papers and has written chapters in eight books. Dr. Sarkar is a registered professional engineer in the state of New York. He received the Best Paper Award of the IEEE Transactions on Electromagnetic Compatibility in 1979. He was an Associate Editor for feature articles of the lEEE Antennas arid Propagation Sociefy Newsletter and was

Dynamic analysis of waveguide structures containing dielectric and metal strips is presented. The analysis utilizes a finite difference frequency domain procedure to reduce the problem to a symmetric matrix eigenvalue problem. Since the matrix is also sparse, the eigenvalue problem can be solved quickly and efficiently using the conjugate gradient method resulting in considerable savings in computer storage and time. Comparison is made with the analytical solution for the loaded dielectric waveguide case. For the microstrip case, we get both waveguide modes and quasi-TEM modes. The quasi-TEM modes in the limit of zero frequency are checked with the static analysis which also uses finite difference. Some of the quasi-TEM modes are spurious. This article describes their origin and discusses how to eliminate them. Numerical results are presented to illustrate the principles.

关键词： Waveguides

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DESIGN FOR TEST USING PARTIAL PARALLEL SCAN

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IEEE TRANSACTIONS ON computer-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1990年第2期9卷 203-211页

作者： LEE, SG SHIN, KG Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

Traditional scan design techniques such as level-sensitive scan design, scan path, and random-access scan suffer from the drawback that the extra test application effort (which includes both time and memory) required is directly proportional to the number of latches and can become quite significant. A scan design technique termed partial parallel scan which reduces test application effort by one to two orders of magnitude is presented. Theoretical and practical aspects of the design method are discussed. The practical use of the partial parallel scan technique has been demonstrated with an LSI circuit and a VLSI circuit designed using silicon compiler tools.< >

关键词： Circuit testing Latches Design for testability Hardware Circuit faults Design automation Switches Design methodology Large scale integration Very large scale integration

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Load sharing in hypercube multicomputer in the presence of node failures 5

Load sharing in hypercube multicomputer in the presence of n...

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5th Distributed Memory computing Conference, DMCC 1990

作者： Chang, Yi-Chieh Shin, Kang G. Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann ArborMI48109-2122 United States

ISBN: (纸本)0818621133

This paper discusses and analyzes two load sharing (LS) issues: adjusting preferred lists and implementing a fault-tolerant mechanism in the presence of node failures. In an early paper, we have proposed to order the nodes in each node's proximity into a preferred list for the purpose of load sharing in distributed real-time systems. The preferred list of each node is constructed in such a way that each node will be selected as the kth preferred node by one and only one other node. Such lists are proven to allow the tasks to be evenly distributed in a system. However, the presence of faulty nodes will destroy the original structure of a preferred list if the faulty nodes are simply skipped in the preferred list. An algorithm is therefore proposed to modify each preferred list to retain its original features regardless of the number of faulty nodes in the system. The communication overhead introduced by this algorithm is shown to be minimal. Based on the modified preferred lists, a simple fault-tolerant mechanism is implemented. Each node is equipped with a backup queue which stores and updates the arriving/completing tasks at its most preferred node. Whenever a node becomes faulty, its most preferred node will treat the tasks in the ba,ckup queue as externally arriving tasks. Our simulation results show that this approach, despite of the simplicity, can reduce the number of task losses dramatically, as compared to the approaches without any faulttolerant mechanism. © 1990 IEEE.

关键词： real time systems

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Traffic routing for multi-computer networks with virtual cut-through capability

Traffic routing for multi-computer networks with virtual cut...

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International Conference on Distributed computing Systems

作者： D.D. Kandlur K.G. Shin Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor USA

The problem of selecting routes for interprocess communication in a network with virtual cut-through capability, while balancing the network load and minimizing the number of times that a message gets buffered, is addressed. The approach taken is to formulate the route selection problem as a minimization problem, with a link cost function that depends on the traffic through the link. The form of this cost function is derived on the basis of the probability of establishing a virtual cut-through route. It is shown that this route selection problem is NP-hard, and so an approximate algorithm that tries to reduce the cost incrementally by rerouting traffic is developed. The performance of this algorithm is evaluated for two popular network topologies: the hypercube and the C-wrapped hexagonal mesh.< >

关键词： Telecommunication traffic Routing Packet switching Delay Cost function Hypercubes Application software Multiprocessor interconnection networks Telecommunication network reliability Communication system control

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A distributed I/O architecture for HARTS

A distributed I/O architecture for HARTS

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Annual International Symposium on computer Architecture, ISCA

作者： K.G. Shin G. Dykema Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The issue of I/O device access in HARTS (Hexagonal Architecture for real-time Systems)-a distributed real-time computer system under construction at the University of Michigan-is explicitly addressed. Several candidate solutions are introduced, explored and evaluated according to cost, complexity, reliability, and performance: (1) 'node-direct' distribution with the intranode bus and a local I/O bus; (2) use of dedicated I/O nodes, which are placed in the hexagonal mesh as regular applications nodes, but which provide I/O services rather than computing services; and (3) use of a separate I/O network; which has led to the proposal of an 'interlaced' I/O network. The interlaced I/O network is intended to provide both high performance without burdening node processors with I/O overhead and a high degree of reliability. Both static and dynamic multiownership protocols are developed for managing I/O device access in this I/O network. The relative merits of the two protocols are explored, and the performance and accessibility which each provides are simulated.< >

关键词： real time systems Distributed computing Topology computer architecture Laboratories Costs Proposals Access protocols Hypercubes computer networks

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Design of a Knowledge-Based Controller for Intelligent Control Systems

Design of a Knowledge-Based Controller for Intelligent Contr...

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American Control Conference (ACC)

作者： Kang G. Shin Xianzhong Cui Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

A hierarchical knowledge-based controller is proposed to improve the performance of complex control systems, such as robots. Unlike parameter- and performance- adaptive controllers, this controller is designed only to modify the reference input of a low-level servo controller. Because the internal parameters and structure of the low-level controller are not affected, commercial servo controllers can be made to perform more sophisticated tasks than originally intended. The principle of the knowledge-based controller, modification of the reference input, knowledge representation, existence of the solution, and analyses of the controller's stability and tracking error are described in detail. A self-tuning multiple-step predictor is designed as a part of the controller to eliminate the undesirable effects of system time delay. Both linear and nonlinear example control systems are tested via extensive simulations and have all shown promising performances.

关键词： Control systems Intelligent control Servomechanisms Robots Programmable control Adaptive control Knowledge representation Stability analysis Error correction Delay effects

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Load Sharing In Hypercube Multicomputers In The Presence Of Node Failures

Load Sharing In Hypercube Multicomputers In The Presence Of ...

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Distributed Memory computing Conference

作者： Yi-Chieh Chang Kang G. Shin Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

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