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IEEE International Conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： Y.-C. Chang K.G. Shin Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The module-sliced approach is realized in a reconfigurable fault-tolerant segmented array processor (RFTSAP). The basic building block of RFTSAP is a node which consists of a processor, local memory, and a programmable I/O unit (PIOU). The PIOU allows any group of processors to be combined to perform the functions of a large processor module. The yield of a large processor module can be improved 2 to 4 times compared to that of approaches not using the module-sliced method.< >

关键词： Very large scale integration Switches Microprocessors Fault tolerance Registers Strontium Laboratories Redundancy Process control computer architecture

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An efficient design of embedded memories and their testability analysis using Markov chains

An efficient design of embedded memories and their testabili...

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International Conference on Wafer Scale Integration

作者： P. Mazumder Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

A design strategy for efficient and comprehensive random testing of embedded random-access memory (RAM), where the address, read/write, and data input lines are not directly controllable and the data output lines are not externally observable, is presented. Unlike conventional approaches which use a linear feedback shift register (LFSR) to generate a signature and a register to store the reference fault-free signature, this technique uses a testable design which both accelerates the test by a factor of 0.5 square root n in an n-bit RAM and improves the test reliability by eliminating the LFSR. The problem of memory initialization has been elegantly circumvented by using word-line flag registers. An in-depth and comprehensive analysis of the functional faults, such as stuck-at, coupling, and pattern-sensitive, is performed. The analysis shows that, in order to test a 1-Mb RAM for common functional faults, the technique needs only 1 s, as opposed to about an hour needed by the conventional random testing.< >

关键词： Random access memory Circuit testing Read-write memory Circuit faults Registers Built-in self-test Life estimation Vectors Gold Sequential analysis

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Message communications in a distributed real-time system with a polled bus

Message communications in a distributed real-time system wit...

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Annual Hawaii International Conference on System sciences (HICSS)

作者： K.G. Shin Y. Muthuswamy Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

High-speed message communications is addressed. Each node in the system consists of multiple processors interconnected by a broadcast bus, but the individual nodes are interconnected by an arbitrary network. The concept of a poll number is proposed to control the access to an intranode bus, minimizing the probability of real-time messages missing their deadlines. When a task generates a time-constrained message, a poll number associated with the message is computed on the basis of the message deadline and the task priority. When the bus is free, the various tasks at a node which desire to use the bus write the poll number onto the bus and read it back, one bit at a time, starting from the most significant bit. If at any time the bit read back is different from the bit written, then that particular task drops out of the competition for the bus. The mechanism provides for not only decentralized control of the intranode bus, but also a high degree of flexibility in scheduling messages by different ways of generating poll numbers. The probability of a message missing its deadline in a token bus is found to be much higher than in a polled bus.< >

关键词： real time systems Communication system control Control systems time factors Automatic control Process control Laboratories Broadcasting Distributed control Job shop scheduling

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Static allocation of periodic tasks with precedence constraints in distributed real-time systems

Static allocation of periodic tasks with precedence constrai...

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International Conference on Distributed computing Systems

作者： D.-T. Peng K.G. Shin Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

Using two branch-and-bound (B&B) algorithms, an optimal solution is proposed to the problem of allocating (or assigning with the subsequent scheduling considered) periodic tasks to a set of heterogeneous processing nodes (PNs) of a distributed real-time system. The allocation objective is to minimize the maximum normalized task response time, called the system hazard, subject to precedence constraints among the tasks to be allocated. First, the task system is modeled with a task graph, which describes computation and communication modules as well as the precedence constraints among them. Second, the exact system hazard of a complete assignment is determined so that an optimal assignment can be derived. This exact cost is obtained by optimally scheduling the modules assigned to each PN with a B&B algorithm guided by the dominance relationship between simultaneously schedulable modules. Third, to reduce the amount of computation needed for an optimal assignment, a lower-bound system hazard that is obtainable with a polynomial time algorithm is derived.< >

关键词： real time systems Scheduling algorithm Delay Processor scheduling Hazards Cost function Distributed computing Laboratories Polynomials time factors

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A floating communication processor architecture in a distributed real-time system

A floating communication processor architecture in a distrib...

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Annual Hawaii International Conference on System sciences (HICSS)

作者： K.G. Shin Y. Muthuswamy Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The issues involved in providing hardware communication support at each mode in a distributed real-time system are studied. First, a general architecture for each node of the system is described. An algorithm for message handling by dedicated hardware called a communication processor (CP) is proposed, to maximize the number of requests handled over the various constraints. A floating CP architecture is proposed, to maximize the number of requests handled under the various constraints. A floating CP architecture is proposed to maximize the utilization of the processors at a node and provide greater fault-tolerance in the system.< >

关键词： real time systems Hardware computer architecture Distributed computing Concurrent computing Laboratories Fault tolerant systems Message passing Data structures Bandwidth

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A microprogrammable VLSI routing controller for HARTS

A microprogrammable VLSI routing controller for HARTS

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IEEE International Conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： J.W. Dolter P. Ramanathan K.G. Shin Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The design and implementation of a VLSI routing controller for use in the Hexagonal Architecture for real-time Systems (HARTS), which is currently being built, are presented. The routing controller is a microprogrammed unit designed to function as an intelligent front-end interface for the interconnection network. Unlike other routine controllers known to date, this routing controller allows for the flexibility to investigate several low-level routing algorithms by downloading the appropriate microcode into the routing controller. The design was carried out using the combination of Seattle Silicon Technology's silicon compiler and Mentor Graphic's schematic capture and simulation tools. The implementation is targeted for a 64-pin package using a 1.2- mu m CMOS process.< >

关键词： Very large scale integration Routing Control systems real time systems Intelligent networks Multiprocessor interconnection networks CMOS technology Silicon compiler Packaging CMOS process

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A clock distribution scheme for nonsymmetric VLSI circuits

A clock distribution scheme for nonsymmetric VLSI circuits

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IEEE International Conference on computer-Aided Design

作者： P. Ramanathan K.G. Shin Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The authors propose a clock distribution scheme that minimizes the difference in the length of clock lines, which is the foremost factor responsible for clock skew in a VLSI circuit. The scheme uses the hierarchy created by the clock buffers to parallelize the distribution of the clock signal. At each hierarchical level, an exhaustive search of paths with intelligent pruning is used to determine the optimal layout of clock lines at that level. Unlike other related work in this area, both delay and skew are taken into account in determining the layout.< >

关键词： Clocks Very large scale integration Circuits Delay Timing Uncertainty NASA Laboratories Control systems Digital systems

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Task Migration In Hypercube Multiprocessors

Task Migration In Hypercube Multiprocessors

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Annual International Symposium on computer Architecture, ISCA

作者： Ming-Syan Chen Kang G. Shin The University of Michigan Department of Electrical Engineering and Computer Science Real-Time Computing Laboratory University슠of슠Michigan Ann Arbor MI USA

Allocation and deallocation of subcubes usually result in a fragmented hypercube where even if a sufficient number of hypercube nodes are available, they do not form a subeube large enough to execute an incoming task. As the fragmentation in conventional memory allocation can be handled by memory compaction, the fragmentation problem in a hypercube can be solved by task migration, i.e., relocating tasks within the hypercubc to remove the fragmentation. The procedure for task migration closely depends on the subcube allocation strategy used, since active tasks must be relocated in such a way that the availability of subcubcs can be detected by that allocation strategy. In this paper, we develop a task migration strategy for the sub cube allocation policy based on the binary reflected Gray code. A goal configuration (of destination subeubes) without fragmentation is determined first. Then, the node-mapping between the source and destination subcubes is derived. Finally, a routing procedure to achieve shortest deadlock-free paths for relocating tasks is developed.

关键词： Hypercubes Permission Compaction Reflective binary codes Laboratories Routing System recovery Concurrent computing computer industry Encoding

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Evaluation of fault-tolerant systems with nonhomogeneous workloads

Evaluation of fault-tolerant systems with nonhomogeneous wor...

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International Symposium on Fault-Tolerant computing (FTCS)

作者： B.E. Aupperle J.F. Meyer L. Wei Computing Research Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

A methodology is presented for evaluating fault-tolerant systems when workloads and fault arrivals are not time-homogeneous. Of particular interests are systems whose environments vary considerably between different utilization phases of random duration. In such cases, evaluations of overall system performability must account for the corresponding differences in workload effects, especially with regard to fault recovery. The proposed methodology uses analytic techniques based on Markov processes and stochastic activity networks. Examples of evaluation studies, using this approach, are presented. These include evaluation of a system wherein self-exercising is varied between phases of passive and active use.< >

关键词： Fault tolerant systems Context modeling Performance evaluation Stochastic processes System performance Software measurement Markov processes Software reliability Software testing Hardware

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THE AEGIS DATA BUS EXPERIMENT

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NAVAL ENGINEERS JOURNAL 1989年第5期101卷 53-58页

作者： FRINK, JG VERVEN, DM John G. Frink is an assistant group supervisor in the Fleet Systems Department of The Johns Hopkins University Applied Physics Laboratory. He received his B.S. degree in physics from Michigan State University in 1968 and the M.S. degree in computer science from the University of Maryland in 1971. Mr. Frink worked at the Naval Surface Weapons Center White Oak Laboratory on a variety of weapons systems before joining the Applied Physics Laboratory in 1978. Mr. Frink has supervised the development of a large scale battle group simulation that successfully employs the receiver selection paradigm described herein on a hardware suite composed of an extensible number of (currently 15) processors. David M. Verven is a senior electrical engineer in the Fleet Systems Department of The Johns Hopkins University Applied Physics Laboratory. He received the B.S. degree in electrical engineering from the University of Maryland College Park in 1979 and the M. S. degree in the same discipline from The Johns Hopkins University in 1984. Mr. Verven joined the Applied Physics Laboratory in 1979 and initially worked on analysis of Navy sensor systems. In 1981 he was the AN/SPS-49 test team leader for the New Threat Upgrade (NTU) combat system land-based test. In 1982 he became involved in the development of the BBWRS system. Currently he is involved in real-time computer program development for the CEP project.

This paper documents an experiment performed by The Johns Hopkins University Applied Physics laboratory to measure the effect of inserting a data bus into a combat system. The experiment was conducted at the Aegis computer Center located at the Naval Surface Weapons Center in Dahlgren, Virginia (NSWC/DL). The purpose of the experiment was to determine whether or not the Aegis Weapon System (the core of the Aegis Combat System) could be operated with a portion of its point-to-point interelement cables replaced by a data bus. The data bus chosen for the experiment employs message broadcasting with receiver selection. A primary goal of the experiment was to minimize the amount of Aegis computer program changes required to accommodate the data bus. The results presented in this paper will show that the experiment was a success. Key certification tests were passed with no computer program changes to the tactical elements and minimal changes in the Aegis tactical executive (ATES) program (less than 110 words changed).

关键词： Data Transmission Equipment

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