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THE COMMAND SUPPORT AT-SEA EXPERIMENT

NAVAL ENGINEERS JOURNAL 1990年第3期102卷 25-36页

作者： BUSCHER, DJ SUNDAY, DM David J. Buscher:is an electrical engineer on the Principal Professional Staff of the Fleet Systems Department of The Johns Hopkins University Applied Physics Laboratory. He earned his BS degree in electrical engineering from Villanova University in 1967 an MSEE degree from the University of Maryland in 1972 and an MS degree in technical management from The Johns Hopkins University in 1985. He was the lead engineer on the Command Support At-Sea Experiment Project. He started his career in 1967 with the U.S. Army Harry Diamond Laboratory working on computer and communications projects. During this time he worked in Vietnam with the United States Army Vietnam Science Advisor Office. Since joining JHU/APL in 1978 he has worked on a variety of projects associated with computer graphics hospital patient information systems computer networks autonomous underwater vehicles and satellite communications. He is currently assistant group supervisor of the Computer Systems Group. Daniel M. Sunday:is a mathematician on the Principal Professional Staff of the Fleet Systems Department of The Johns Hopkins University Applied Physics Laboratory. He earned his Ph.D. in mathematics from the University of Minnesota in 1971 and did postdoctoral research on neural networks at the University of California at Berkeley. Since joining JHU/APL in 1980 Dr. Sunday has worked as a designer and developer of software systems with emphasis on medical imaging interactive graphics natural language interfaces and software standards. He was the network designer for the Headquarters Integrated Office System (HIOS) Network for the Army at the Pentagon. He is currently the lead software engineer on the Command Support At-Sea Experiment Project.

The Command Support At-Sea Experiment (CS@SE) provides experimental advanced graphics display systems consisting of large screen color displays and operator console color displays in the combat information center (CIC) of an Aegis cruiser and in the tactical flag command center (TFCC) of an aircraft carrier. CS@SE systems are designed to prototype potential command support capabilities in an at-sea environment to validate and refine requirements for planned production system upgrades. These systems use sophisticated color graphics techniques to provide real-time tactical displays that improve the availability of information to an operator by reducing clutter through the use of color, area fill, transparen overlays and intensity coding of track symbols. Interfaces wen developed with the Aegis Display System (ADS), Shipboarc Gridlock System with Auto-correlation (SGS/AC), Flag Dats Display System (FDDS) and Tomahawk Engagement Planning and Exercise Evaluation System (TEPEE) that provided the data for the presentation of a tactical display. Display elements included both real-time and over-the-horizon (OTH) surface track data, velocity leaders, tags, uncertainty ellipses, and history trails. The display also included filled land masses, country boundaries, commercial airways, cities, graphics overlays (i.e., operational areas), weapon system missile performance contours, and engagement plans. This paper describes the experiment, its installation and integration into the shipboard environments of an Aegis cruiser (USS Leyte Gulf ) and an aircraft carrier (USS America , its usage by the ships companies and embarked staffs, and the experiment result! and findings. Key conclusions of the experiment are: 1 Advanced graphics color displays can significantly enhance the ability of the warfighter to assimilate a complex tactical display. 2 Both ships reported a requirement for a correlated OTH and real-time track display with the ability to clearly differentiate the two types

关键词： computer Graphics

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Message routing in HARTS with faulty components

Message routing in HARTS with faulty components

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International Symposium on Fault-Tolerant computing (FTCS)

作者： A. Olson K.G. Shin Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The authors develop a routing scheme in two steps for a wrapped hexagonal mesh, called HARTS (hexagonal architecture for real-time systems), which ensures the delivery of every message as long as there is a path between its source and destination. The scheme can also detect the nonexistence of a path between a pair of nodes in a finite amount of time. Moreover, the scheme requires each node in HARTS to know only the state (faulty or not) of each of its own links. The performance of the simple routing scheme is simulated for three- and five-dimensional H-meshes while the physical distribution of faulty components is varied. It is shown that a shortest path between the source and the destination of each message is taken with a high probability, and a path, if one exists, is usually found very quickly.< >

关键词： Routing Laboratories Fault tolerant systems Computational modeling Distributed computing Parallel processing Hypercubes Broadcasting NASA Contracts

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A module-sliced approach for high yield VLSI/WSI processors

A module-sliced approach for high yield VLSI/WSI processors

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IEEE International Conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： Y.-C. Chang K.G. Shin Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The module-sliced approach is realized in a reconfigurable fault-tolerant segmented array processor (RFTSAP). The basic building block of RFTSAP is a node which consists of a processor, local memory, and a programmable I/O unit (PIOU). The PIOU allows any group of processors to be combined to perform the functions of a large processor module. The yield of a large processor module can be improved 2 to 4 times compared to that of approaches not using the module-sliced method.< >

关键词： Very large scale integration Switches Microprocessors Fault tolerance Registers Strontium Laboratories Redundancy Process control computer architecture

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Minimum time trajectory planning for dual robot systems

Minimum time trajectory planning for dual robot systems

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IEEE Conference on Decision and Control

作者： K.G. Shin Q. Zheng Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The problem of planning minimum time collision-free trajectories for a dual robot system is addressed. It is shown that this problem can be solved by first planning the minimum time trajectory for each robot without considering the existence of the other and then combining the two individual trajectories. This combination is accomplished by delaying one of the two trajectories in such a way that the time required for the coordinated motion of the two robots is minimized while avoiding collision between them. The optimality of the method is rigorously proved, the practical aspects of its realization are discussed, and example is presented.< >

关键词： Trajectory Robot kinematics Path planning Robot sensing systems Motion planning Laboratories computer science Delay effects Artificial intelligence Productivity

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An efficient design of embedded memories and their testability analysis using Markov chains

An efficient design of embedded memories and their testabili...

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International Conference on Wafer Scale Integration

作者： P. Mazumder Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

A design strategy for efficient and comprehensive random testing of embedded random-access memory (RAM), where the address, read/write, and data input lines are not directly controllable and the data output lines are not externally observable, is presented. Unlike conventional approaches which use a linear feedback shift register (LFSR) to generate a signature and a register to store the reference fault-free signature, this technique uses a testable design which both accelerates the test by a factor of 0.5 square root n in an n-bit RAM and improves the test reliability by eliminating the LFSR. The problem of memory initialization has been elegantly circumvented by using word-line flag registers. An in-depth and comprehensive analysis of the functional faults, such as stuck-at, coupling, and pattern-sensitive, is performed. The analysis shows that, in order to test a 1-Mb RAM for common functional faults, the technique needs only 1 s, as opposed to about an hour needed by the conventional random testing.< >

关键词： Random access memory Circuit testing Read-write memory Circuit faults Registers Built-in self-test Life estimation Vectors Gold Sequential analysis

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Message communications in a distributed real-time system with a polled bus

Message communications in a distributed real-time system wit...

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Annual Hawaii International Conference on System sciences (HICSS)

作者： K.G. Shin Y. Muthuswamy Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

High-speed message communications is addressed. Each node in the system consists of multiple processors interconnected by a broadcast bus, but the individual nodes are interconnected by an arbitrary network. The concept of a poll number is proposed to control the access to an intranode bus, minimizing the probability of real-time messages missing their deadlines. When a task generates a time-constrained message, a poll number associated with the message is computed on the basis of the message deadline and the task priority. When the bus is free, the various tasks at a node which desire to use the bus write the poll number onto the bus and read it back, one bit at a time, starting from the most significant bit. If at any time the bit read back is different from the bit written, then that particular task drops out of the competition for the bus. The mechanism provides for not only decentralized control of the intranode bus, but also a high degree of flexibility in scheduling messages by different ways of generating poll numbers. The probability of a message missing its deadline in a token bus is found to be much higher than in a polled bus.< >

关键词： real time systems Communication system control Control systems time factors Automatic control Process control Laboratories Broadcasting Distributed control Job shop scheduling

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Static allocation of periodic tasks with precedence constraints in distributed real-time systems

Static allocation of periodic tasks with precedence constrai...

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International Conference on Distributed computing Systems

作者： D.-T. Peng K.G. Shin Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

Using two branch-and-bound (B&B) algorithms, an optimal solution is proposed to the problem of allocating (or assigning with the subsequent scheduling considered) periodic tasks to a set of heterogeneous processing nodes (PNs) of a distributed real-time system. The allocation objective is to minimize the maximum normalized task response time, called the system hazard, subject to precedence constraints among the tasks to be allocated. First, the task system is modeled with a task graph, which describes computation and communication modules as well as the precedence constraints among them. Second, the exact system hazard of a complete assignment is determined so that an optimal assignment can be derived. This exact cost is obtained by optimally scheduling the modules assigned to each PN with a B&B algorithm guided by the dominance relationship between simultaneously schedulable modules. Third, to reduce the amount of computation needed for an optimal assignment, a lower-bound system hazard that is obtainable with a polynomial time algorithm is derived.< >

关键词： real time systems Scheduling algorithm Delay Processor scheduling Hazards Cost function Distributed computing Laboratories Polynomials time factors

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A floating communication processor architecture in a distributed real-time system

A floating communication processor architecture in a distrib...

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Annual Hawaii International Conference on System sciences (HICSS)

作者： K.G. Shin Y. Muthuswamy Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The issues involved in providing hardware communication support at each mode in a distributed real-time system are studied. First, a general architecture for each node of the system is described. An algorithm for message handling by dedicated hardware called a communication processor (CP) is proposed, to maximize the number of requests handled over the various constraints. A floating CP architecture is proposed, to maximize the number of requests handled under the various constraints. A floating CP architecture is proposed to maximize the utilization of the processors at a node and provide greater fault-tolerance in the system.< >

关键词： real time systems Hardware computer architecture Distributed computing Concurrent computing Laboratories Fault tolerant systems Message passing Data structures Bandwidth

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A microprogrammable VLSI routing controller for HARTS

A microprogrammable VLSI routing controller for HARTS

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IEEE International Conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： J.W. Dolter P. Ramanathan K.G. Shin Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The design and implementation of a VLSI routing controller for use in the Hexagonal Architecture for real-time Systems (HARTS), which is currently being built, are presented. The routing controller is a microprogrammed unit designed to function as an intelligent front-end interface for the interconnection network. Unlike other routine controllers known to date, this routing controller allows for the flexibility to investigate several low-level routing algorithms by downloading the appropriate microcode into the routing controller. The design was carried out using the combination of Seattle Silicon Technology's silicon compiler and Mentor Graphic's schematic capture and simulation tools. The implementation is targeted for a 64-pin package using a 1.2- mu m CMOS process.< >

关键词： Very large scale integration Routing Control systems real time systems Intelligent networks Multiprocessor interconnection networks CMOS technology Silicon compiler Packaging CMOS process

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A clock distribution scheme for nonsymmetric VLSI circuits

A clock distribution scheme for nonsymmetric VLSI circuits

引用

IEEE International Conference on computer-Aided Design

作者： P. Ramanathan K.G. Shin Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The authors propose a clock distribution scheme that minimizes the difference in the length of clock lines, which is the foremost factor responsible for clock skew in a VLSI circuit. The scheme uses the hierarchy created by the clock buffers to parallelize the distribution of the clock signal. At each hierarchical level, an exhaustive search of paths with intelligent pruning is used to determine the optimal layout of clock lines at that level. Unlike other related work in this area, both delay and skew are taken into account in determining the layout.< >

关键词： Clocks Very large scale integration Circuits Delay Timing Uncertainty NASA Laboratories Control systems Digital systems

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