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检索条件"机构=Reconfigurable Computing Systems Lab."

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Custom precision accelerators for energy-efficient image-to-image transformations in motion picture workflows 46

Custom precision accelerators for energy-efficient image-to-...

引用

Applications of Digital Image Processing XLVI 2023

作者： Murphy, Emmet Khandelwal, Shashwat Shanker, Shreejith Reconfigurable Computing Systems Lab. Trinity College Dublin Dublin Ireland

ISBN: (纸本)9781510665620

Image to Image (I2I) transformations have been an integral part of video processing workflows with applications in Image Synthesis for Virtual Productions, Segmentation, and Matting, among others. Over the years, deep learning-based approaches have been enabling new methods and tools for automating parts of the processing pipeline, reducing the human effort i nvolved i n p ost-production w orkflows. Th ese co mpute-intensive models are often accelerated through on-premise or in-cloud GPU instances to improve the responsiveness and latency while expending large amounts of energy in performing these complex transformations. In this work, we present an approach for optimising the energy efficiency of I2 I de ep-learning mo dels us ing qu antised ne ural networks accelerated on a server-style FPGA. We use deep learning-based alpha background matting as the I2I application which is implemented using a U-Net conditional Generative Adversarial Network deep learning model. The model is trained and quantised using Vitis-AI flow from AMD/Xilinx and deployed on a data centre class Alveo U50 FPGA device. Our results show that the quantised model on the FPGA achieves a 1.14× higher throughput for inference acceleration while consuming 11× lower energy consumption per inference when compared to a GPU-accelerated version of the model on a 3080-Ti, while generating nearly identical results with an average IoU > 0.95 across multiple user images at 1080p and 4K resolutions. Additionally, offloads to the FPGA device can be seamlessly integrated into widely used motion picture tools like NUKE with minimal effort. With most cloud providers integrating heterogenous platforms (including FPGAs) into systems, we envision that this work paves the way for more efficient utilisation of custom precision deep-learning models and FPGA acceleration in deep learning-based motion picture workflows. © 2023 SPIE.

关键词： Field programmable gate arrays (FPGA)

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A radix tree router for scalab.e FPGA networks

A radix tree router for scalable FPGA networks

引用

21st International Conference on Field Programmable Logic and Applications, FPL 2011

作者： Kritikos, William V. Rajasekhar, Yamuna Schmidt, Andrew G. Sass, Ron Reconfigurable Computing Systems Lab. University of North Carolina Charlotte United States

ISBN: (纸本)9780769545295

Many FPGA based Network-on-Chip (NoC) and directly connected clusters use routers implemented in the FPGA fabric. Existing projects have optimized the routers for low resource utilization, low latency, and high bandwidth, often at the cost of programmability and manageability. Developers using the existing FPGA networks often have no way to specify a source or destination of a message except by using the physical locations of the nodes in the network. This low level of abstraction limits developer productivity and the ability of the network to adapt to changing conditions. We present an FPGA network that resolves these issues by allowing the developer to use familiar 32-bit addresses similar to an IP address and a router that uses a software managed routing table. The implementation presented here demonstrates similar resource utilization and bandwidth with a minimal increase in latency when compared to existing FPGA router implementations. © 2011 IEEE.

关键词： Routers

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A first analysis of a dynamic Memory Allocation Controller (DMAC) core

A first analysis of a dynamic Memory Allocation Controller (...

引用

2011 Symposium on Application Accelerators in High-Performance computing, SAAHPC 2011

作者： Rajasekhar, Yamuna Sass, Ron Reconfigurable Computing Systems Lab. University of North Carolina Charlotte United States

ISBN: (纸本)9780769544489

Networking performance continues to grow but processor clock frequencies have not. Likewise, the latency to primary memory is not expected to improve dramatically either. This is leading computer architects to reconsider the networking subsystem and the roles and responsibilities of hardware and the operating system. This paper presents the first component of a new networking subsystem where the hardware is responsible for buffering, when necessary, messages without interrupting or involving the operating system. The design is presented and its functionality is demonstrated. The core on an FPGA is exercised with a synthetic stream of messages and the results show that the analytical performance model and measured performance agree. © 2011 IEEE.

关键词： Computer operating systems

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Impact of reconfigurable hardware on accelerating MPI-reduce

Impact of reconfigurable hardware on accelerating MPI-reduce

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2010 International Conference on Field-Programmable Technology, FPT'10

作者： Gao, Shanyuan Schmidt, Andrew G. Sass, Ron Reconfigurable Computing Systems Lab. University of North Carolina at Charlotte Charlotte NC United States

ISBN: (纸本)9781424489817

This paper demonstrates the benefits and pit-falls of implementing the collective communication operation reduce in the reconfigurable resources of an FPGA device across a cluster of all-FPGA compute nodes. Specifically, the communication and computation semantics of the MPI-Reduce call from the de facto Message-Passing Interface have been implemented. Using a synthetic benchmark a cluster of 32 FPGA nodes with a 300 MHz PowerPC processor, custom high speed network, and reduce core is compared against a conventional commodity cluster with 3.2 GHz Xeon processors and Gigabit Ethernet. The design is customized to support performing many reduce operations on small datasets while minimizing the amount of on-chip resources used, which is an increasingly common demand from domain scientists. Speedups of ≈2× to ≈800× are reported over that of a commodity cluster for small datasets, which provides significant motivation to continue the investigation into supporting additional collective communication operations directly in hardware. © 2010 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Architecture and applications for an all-FPGA parallel computer

Architecture and applications for an all-FPGA parallel compu...

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41st International Conference on Parallel Processing Workshops, ICPPW 2012

作者： Rajasekhar, Yamuna Sass, Ron Reconfigurable Computing Systems Lab. University of North Carolina at Charlotte Charlotte NC United States

ISBN: (纸本)9780769547954

The reconfigurable computing Cluster (RCC) project has been investigating unconventional architectures for high end computing using a cluster of FPGA devices connected by a high-speed, custom network. Most applications use the FPGAs to realize an embedded System-on-a-Chip (SoC) design augmented with application-specific accelerators to form a message-passing parallel computer. Other applications take a single accelerator core and tessellate the core across all of the devices, treating them like a large virtual FPGA. The experimental hardware has also been used for basic computer research by emulating novel architectures. This article discusses the genesis of the over-arching project, summarizes results of individual investigations that have been completed, and how this approach may prove useful in the investigation of future Exascale systems. © 2012 IEEE.

关键词： Field programmable gate arrays (FPGA)

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A high performance, open source SATA2 core

A high performance, open source SATA2 core

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22nd International Conference on Field Programmable Logic and Applications, FPL 2012

作者： Mendon, Ashwin A. Huang, Bin Sass, Ron Reconfigurable Computing Systems Lab. University of North Carolina at Charlotte Charlotte NC United States

ISBN: (纸本)9781467322560

This paper describes the design and implementation of an open source FPGA-based SATA2 core. It provides the ability to directly interface with hardware cores which is beneficial for high performance and embedded computing applications. Additionally, the core has a bus interface and DMA engine that makes it availab.e to the operating system through a Linux block device driver. Measurements with solid state drives reveal that our FPGA-based implementation achieves performance close to the disks' theoretical peak. In contrast, we find that software overhead on a modern Linux server prevents exploiting the full potential of these high speed storage devices. Native Command Queueing is supported by the core and the performance results highlight its importance in the context of SSDs, especially for small block transfers. The small size of our SATA core (1.5% of the logic resources on a Virtex-6 FPGA) indicates that an on-chip RAID storage system is feasible. © 2012 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Investigating resilient high performance reconfigurable computing with minimally-invasive system monitoring

Investigating resilient high performance reconfigurable comp...

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2010 4th International Workshop on High-Performance reconfigurable computing Technology and Applications, HPRCTA'10, Held in Conjunction with SC10

作者： Huang, Bin Schmidt, Andrew G. Mendon, Ashwin A. Sass, Ron Reconfigurable Computing Systems Lab. Department of Electrical and Computer Engineering University of North Carolina Charlotte NC United States

ISBN: (纸本)9781424495177

As researchers push for Exascale computing, one of the emerging challenges is system resilience. Unlike fault-tolerance which corrects errors, recent reports suggest that resilient systems will need to continue to make progress on an application despite faults. A first step in developing a resilient system is to have robust, scalab.e system monitoring. The work described here presents a novel, minimally-invasive system monitor that operates over a separate network. We analytically characterize the performance for an arbitrary set of nodes and demonstrate a working implementation of the design. We argue that the hardware approach is inherently superior to the ad hoc, software techniques currently employed in practice. © 2010 IEEE.

关键词： Fault tolerance

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Design and utilization of an FPGA cluster to implement a digital wireless channel emulator

Design and utilization of an FPGA cluster to implement a dig...

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22nd International Conference on Field Programmable Logic and Applications, FPL 2012

作者： Buscemi, Scott Sass, Ron Advanced Communication Technologies Lab. SPAWAR Systems Center Atlantic Charleston SC United States Reconfigurable Computing Systems Lab. University of North Carolina at Charlotte Charlotte NC United States

ISBN: (纸本)9781467322560

A Digital Wireless Channel Emulator (DWCE) is a system that is capable of emulating the RF environment for a group of radios. A major issue with current designs is that they do not scale to a large enough number of nodes to emulate meaningful network due to the amount of computations required for such a system. This paper proposes a novel DWCE design based on a cluster of FPGA devices. By decentralizing the signal processing it is possible to increase the availab.e computational resources to the point where they are no longer the limiting factor to scalab.lity. It demonstrates feasibility by analyzing the computational and network requirements of the application and showing how the proposed design meets those needs. The paper also describes the physical design of a new 64 node FPGA cluster that is being manufactured. An implementation on prototype nodes of this cluster demonstrates the machine will support a high fidelity emulation for 32 radios or a lower-fidelity emulation for 128 radios. © 2012 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Improving FPGA design and evaluation productivity with a hardware performance monitoring infrastructure

Improving FPGA design and evaluation productivity with a har...

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2011 International Conference on reconfigurable computing and FPGAs, ReConFig 2011

作者： Schmidt, Andrew G. Sass, Ron Information Sciences Institute University of Southern California United States Reconfigurable Computing Systems Lab. University of North Carolina Charlotte NC United States

ISBN: (纸本)9780769545516

Hardware design with FPGAs can be a daunting task, even for experienced engineers. Even with sophisticated tools and improvements in high-level language to gates approaches, an engineer can expend significant effort simply implementing the design. Often, when the design is evaluated on the FPGA, the performance may not be what was expected. As a result, an engineer may go back and augment the design to include performance monitors to help identify the bottlenecks in the system or to aid in the debugging of the design. This work aims to alleviate this effort. We present the Hardware Performance Monitoring Infrastructure (HwPMI), which includes a collection of software tools and hardware cores that can be used to profile the current design, recommend/insert performance monitors directly into the HDL, and retrieve the monitored data with minimal invasion to the design. This paper reports on the functionality of the tools and the integration of the hardware cores into existing designs. © 2011 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Merging programming models and on-chip networks to meet the programmable and performance needs of multi-core systems on a programmable chip

Merging programming models and on-chip networks to meet the ...

引用

International Conference on reconfigurable computing and FPGAs

作者： Schmidt, Andrew G. Kritikos, William V. Sass, Ron Anderson, Erik K. French, Matthew Reconfigurable Computing Systems Lab. Univ. of North Carolina Charlotte United States Information Science Institute University of Southern California United States

ISBN: (纸本)9780769543147

The reconfigurable Data-Stream Hardware Software ARChitecture (Redsharc) is a programming model and network-on-a-chip solution designed to scale to meet the performance needs of multi-core systems on a programmable chip. Redsharc uses an abstract API that allows programmers to develop systems of simultaneously executing kernels, in software or hardware, that communicate over a seamless interface. To support high performance systems with numerous hardware kernels, Redsharc incorporates two on-chip networks that directly mimic the API. Our results show that Redsharc running at 200 MHz, 32-bit data widths can achieve 800 MBps per stream from hardware to hardware, 480 MBps for a software to hardware stream, and between 20 MBps and 400 MBps for random access data in blocks, regardless of the number of kernels in the system. © 2010 IEEE.

关键词： Application programming interfaces (API)

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