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Real time ARM-based traffic Level of Service classification system 13

Real time ARM-based traffic Level of Service classification ...

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13th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, ECTI-CON 2016

作者： The, Phuc Nguyen Nguyen Hoang, Ngoc Anh Nguyen, Tung Anh Xuan, Them Nguyen Tung, Lam Le Viet-Hoa, Do Ngoc, Nam Pham Embedded Systems and Reconfigurable Computing Laboratory School of Electronics and Telecommunications Hanoi University of Science and Technology Viet Nam

ISBN: (纸本)9781467397490

Traffic Level of Service (LOS) information is crucial for traffic management systems, especially in urban areas. One method to estimate traffic LoS is to use a central server system to process traffic images captured by road side cameras. However, this approach requires a high performance server system as well as high network throughput to transmit images from the cameras to the server, which results in very high system deployment cost. In this paper, we propose a cost effective distributed solution using smart cameras each of which is equipped with a low cost ARM microprocessor to estimate the LOS from the captured traffic images. The LOS of a road estimated by a corresponding camera will then be sent to a traffic information server. In this study, LOS is determined based on the average traffic flow speed and the road occupancy. The Lucas Kanade optical flow method is used to estimate the speed of the traffic flow. In order to have a real time processing on a low cost platform, the whole LOS estimation algorithm has been optimized. The experimental results show that our optimized implementation can process traffic images in real time on an ARM Cortex-A8 platform and is 4 times faster than an OpenCV based implementation on the same platform. © 2016 IEEE.

关键词： Cameras

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A simple camera calibration method for vehicle velocity estimation 12

A simple camera calibration method for vehicle velocity esti...

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12th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, ECTI-CON 2015

作者： Do, Viet-Hoa Nghiem, Le-Hoa Thi, Ngoc Pham Ngoc, Nam Pham Embedded Systems and Reconfigurable Computing Laboratory School of Electronics and Telecommunications Hanoi University of Science and Technology Viet Nam

ISBN: (纸本)9781479979608

Camera calibration is an essential step in vision-based vehicle speed measurement systems. In this paper, a simple, easy, and robust camera calibration method for vehicle speed measurement is proposed. First, the camera is installed at any position that can cover the desired traffic images. After that, an equilateral triangle is drawn on the ground within the view scene of the camera as a reference object. Then, the image of the triangle captured by the traffic camera is used to determine the camera parameters. The main advantage of our method is that it requires very little effort put into installing the camera and can be used in any road conditions. In order to prove the advantages of our method, we use the found camera parameters with the motion vectors of traffic video frames estimated by the optical flow algorithm to calculate the real moving speed of vehicles. Our experimental results have shown that the proposed method is reliable and easy to use. © 2015 IEEE.

关键词： Optical flows

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A Radix Tree Router for Scalable FPGA Networks

A Radix Tree Router for Scalable FPGA Networks

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International Conference on Field Programmable Logic and Applications

作者： William V. Kritikos Yamuna Rajasekhar Andrew G. Schmidt Ron Sass Reconfigurable Computing Systems Laboratory University of North Carolina Charlotte USA

Many FPGA based Network-on-Chip (NoC) and directly connected clusters use routers implemented in the FPGA fabric. Existing projects have optimized the routers for low resource utilization, low latency, and high bandwidth, often at the cost of programmability and manageability. Developers using the existing FPGA networks often have no way to specify a source or destination of a message except by using the physical locations of the nodes in the network. This low level of abstraction limits developer productivity and the ability of the network to adapt to changing conditions. We present an FPGA network that resolves these issues by allowing the developer to use familiar 32-bit addresses similar to an IP address and a router that uses a software managed routing table. The implementation presented here demonstrates similar resource utilization and bandwidth with a minimal increase in latency when compared to existing FPGA router implementations.

关键词： Field programmable gate arrays Routing Bandwidth System-on-a-chip Software Computer architecture IP networks

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Impact of off-chip memories on HLS-generated circuits 6

Impact of off-chip memories on HLS-generated circuits

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6th International Workshop on FPGAs for Software Programmers, FSP 2019, co-located with International Conference on Field Programmable Logic and Applications, FPL 2019

作者： Abhi, D.R. Sass, Ron Schmidt, Andrew Reconfigurable Computing Systems Laboratory University of North Carolina at Charlotte CharlotteNC United States Information Sciences Institute University of Southern California ArlingtonVA United States

ISBN: (纸本)9783800750467

High-Level Synthesis (HLS) has been proposed as a comfortable high-level programming languages solution to overcome the insurmountable barrier of hardware design and Hardware Description Languages (HDLs). While academic and commercial tools have made huge strides, nearly all of these tools focus exclusively on the computation and the data path. Rarely do they directly address the memory subsystem and its impact on the overall performance. At best, the programmer can assist the tools with directives/pragmas but these are designed to change the data path and only indirectly impact the memory subsystem performance. With introduction of next-generation memories such as HMC, HBM etc. these directives will (unintentionally) exacerbate memory issues. In this we paper, we explore the impact on off-chip memory by designing different kernels with different optimizations. We test these kernels with two different commercial HLS flow on three different platforms consisting DDR3 and DDR4 memory. Based on this sweeping study and the requirements of next-generation memory, we design a hardware-software methodology to improve the off-chip memory access. The results suggest that this is suitable for next-generation memory and a lot opportunity to improve the methodology. © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach

关键词： High level synthesis

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Volcan: System Integration of HLS and HMC on FPGAs

Volcan: System Integration of HLS and HMC on FPGAs

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2019 International Conference on reconfigurable computing and FPGAs, ReConFig 2019

作者： Rajagopala, Abhi D. Sass, Ron Schmidt, Andrew G. Reconfigurable Computing Systems Laboratory University of North Carolina at Charlotte CharlotteNC United States Information Sciences Institute University of Southern California ArlingtonVA United States

ISBN: (纸本)9781728119571

High-Level Synthesis (HLS) is a process that translates traditional software languages (C/C++/Java) into either a hardware description language representation or a netlist representation that, ultimately, can be implemented on an FPGA device, for example. The original goal was to make advanced computing accelerators accessible to embedded computing systems programmers. However, the technology has attracted the interest of high-performance computing (HPC) programmers as well. This would be a huge benefit because labor statistics suggest that every year 10x as many software programmers graduate for every hardware designer [1]. However, HPC programmers use large in-core datasets versus the transient, streaming data sets that are common in embedded systems. Looking forward, it is appropriate to explore the behavior of HLS with next-generation memory technologies, like the Hybrid Memory Cube (HMC). © 2019 IEEE.

关键词： High level synthesis

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Performance evaluation of Sparse Matrix-Matrix Multiplication

Performance evaluation of Sparse Matrix-Matrix Multiplicatio...

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International Conference on Field Programmable Logic and Applications

作者： Shweta Jain-Mendon Ron Sass Reconfigurable Computing Systems Laboratory University of North Carolina Charlotte USA

The conventional matrix multiplication algorithms that are suitable for dense matrices do not perform well on the corresponding Sparse Matrix-Matrix Multiplication (SMMM) operation. In particular, they do not utilize the sparsity of the matrix. This paper describes a new technique for performing the SMMM operation using a novel storage format for sparse matrices. To demonstrate the feasibility of this technique, the SMMM operation is implemented on an FPGA and various parameters that affect the performance of the design are explored.

关键词： Sparse matrices Arrays Field programmable gate arrays Random access memory Finite element analysis Hardware

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An Extensible and Portable Tool Suite for Managing Multi-Node FPGA systems

An Extensible and Portable Tool Suite for Managing Multi-Nod...

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Annual IEEE Symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Yamuna Rajasekhar Rahul R. Sharma Ron Sass Reconfigurable Computing Systems Laboratory University of North Carolina Charlotte USA

Current trends in reconfigurable computing point to an ever-increasing need for logic resources. This has led to the development and deployment of systems consisting of multiple FPGAs. These systems are advancing from scores of FPGAs to hundreds of FPGAs. Programming and administering these kind of systems while maintaining a non-intrusive physical footprint is expected to remain a continuing challenge. Future systems demand lower FPGA configuration and initialization turn-around times while maintaining a high degree of resource availability. Also, support for new configuration methodologies and portability to the latest generations of FPGA platforms is required. This paper describes an improved suite of tools with new features like job scheduling, bit stream management, multiple session control, debugging capabilities and remote access that will enable large scale High Performance reconfigurable computing.

关键词： Field programmable gate arrays Power capacitors Servers Linux Ash Protocols Computer architecture

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A case study of streaming storage format for sparse matrices

A case study of streaming storage format for sparse matrices

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International Conference on reconfigurable computing and FPGAs (ReConFig)

作者： Shweta Jain-Mendon Ron Sass Reconfigurable Computing Systems Laboratory University of North Carolina Charlotte USA

The Field-Programmable Gate Array is an excellent match for the sparse matrix-vector multiply operation because of its enormous computational capacity and its ability to build a custom memory hierarchy that matches the memory access patterns of the operation. This paper describes a streaming sparse matrix format and a custom memory subsystem that decodes it on-the-fly for multiple compute units. Results show that the proposed design is very efficient and allows the sparse matrix to be streamed sequentially from off-chip RAM. On a Xilinx Virtex-4 device, this results in an average of 58% memory-bandwidth efficiency for one compute unit and 70% memory-bandwidth efficiency for two compute units. The design is capable of achieving an average of 47% of theoretical peak floating-point performance for each compute unit.

关键词： Indexes Sparse matrices Bandwidth Vectors Performance evaluation Finite element methods Decoding

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Exploring hardware work queue support for lightweight threads in MPSoCs

Exploring hardware work queue support for lightweight thread...

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International Conference on reconfigurable computing and FPGAs (ReConFig)

作者： Rahul R Sharma Yamuna Rajasekhar Ron Sass Reconfigurable Computing Systems Laboratory University of North Carolina Charlotte USA

Fine-grain thread parallelism using task based programming models are a new trend in achieving massively parallel computations. Often, software pre-fetching and queuing mechanisms for managing these dynamic environments are inadequate, failing to keep the processor cores busy with computation. At the same time, the CPU-memory performance gap is getting worse and this puts a strain on memory subsystem to keep cores in a busy state. We describe a hardware based pre-fetching and queuing mechanism aimed at assisting the over-subscription of very lightweight threads per core. Experiments with a soft processor and a reconfigurable accelerator core are reported. The hardware demonstrates the ability to block on out-of-order memory transactions and alleviates the software bottleneck.

关键词： Instruction sets Hardware Throughput Registers Random access memory Switches Memory management

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Architecture and Applications for an All-FPGA Parallel Computer

Architecture and Applications for an All-FPGA Parallel Compu...

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International Conference on Parallel Processing Workshops (ICPPW)

作者： Yamuna Rajasekhar Ron Sass Reconfigurable Computing Systems Laboratory University of North Carolina Charlotte Charlotte USA

The reconfigurable computing Cluster (RCC) project has been investigating unconventional architectures for high end computing using a cluster of FPGA devices connected by a high-speed, custom network. Most applications use the FPGAs to realize an embedded System-on-a-Chip (SoC) design augmented with application-specific accelerators to form a message-passing parallel computer. Other applications take a single accelerator core and tessellate the core across all of the devices, treating them like a large virtual FPGA. The experimental hardware has also been used for basic computer research by emulating novel architectures. This article discusses the genesis of the over-arching project, summarizes results of individual investigations that have been completed, and how this approach may prove useful in the investigation of future Exascale systems.

关键词： Field programmable gate arrays Computer architecture Hardware Switches Computers System-on-a-chip

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