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Impact of reconfigurable hardware on accelerating MPI_Reduce

Impact of reconfigurable hardware on accelerating MPI_Reduce

引用

IEEE International Conference on Field-Programmable Technology (FPT)

作者： Shanyuan Gao Andrew G. Schmidt Ron Sass Reconfigurable Computing Systems Laboratory University of North Carolina Charlotte Charlotte NC USA

This paper demonstrates the benefits and pit-falls of implementing the collective communication operation reduce in the reconfigurable resources of an FPGA device across a cluster of all-FPGA compute nodes. Specifically, the communication and computation semantics of the MPI_Reduce call from the de facto Message-Passing Interface have been implemented. Using a synthetic benchmark a cluster of 32 FPGA nodes with a 300 MHz PowerPC processor, custom high speed network, and reduce core is compared against a conventional commodity cluster with 3.2 GHz Xeon processors and Gigabit Ethernet. The design is customized to support performing many reduce operations on small datasets while minimizing the amount of on-chip resources used, which is an increasingly common demand from domain scientists. Speedups of ≈2x to ≈800x are reported over that of a commodity cluster for small datasets, which provides significant motivation to continue the investigation into supporting additional collective communication operations directly in hardware.

关键词： Field programmable gate arrays Hardware Software Topology Optimization Peer to peer computing Ethernet networks

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FPGA-based three-body molecular dynamics simulator

FPGA-based three-body molecular dynamics simulator

引用

International Conference on High Performance computing & Simulation (HPCS)

作者： Robin Pottathuparambil Ron Sass Reconfigurable Computing Systems Laboratory University of North Carolina Charlotte Charlotte NC USA

The computer simulation of three-body potentials using the Stillinger-Weber method has been extensively used in the study of three-body molecular forces between partially rigid molecules such as silicon. The Stillinger-Weber method of computing three-body interactions is generally computationally intense. This paper presents a FPGA-based framework that is designed and implemented on a Virtex 4 that can be used to compute Stillinger-Weber potential. This framework extends the PowerPC instruction set to include vector operations and a custom datapath. Design details of the framework along with initial performance results with two well-known data sets are also presented. The results show that FPGA design is competitive with current microprocessors on small problems sizes and with only half of the algorithm implemented. As the problem size increases, the results suggest the FPGA-based design will gain a significant performance advantage. Coding the second half of the algorithm will increase the on-chip parallelism as well.

关键词： Force Program processors Computational modeling Silicon Field programmable gate arrays Arrays Heuristic algorithms

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A high performance, open source SATA2 core

A high performance, open source SATA2 core

引用

International Conference on Field Programmable Logic and Applications

作者： Ashwin A. Mendon Bin Huang Ron Sass Reconfigurable Computing Systems Laboratory University of North Carolina Charlotte Charlotte NC USA

This paper describes the design and implementation of an open source FPGA-based SATA2 core. It provides the ability to directly interface with hardware cores which is beneficial for high performance and embedded computing applications. Additionally, the core has a bus interface and DMA engine that makes it available to the operating system through a Linux block device driver. Measurements with solid state drives reveal that our FPGA-based implementation achieves performance close to the disks' theoretical peak. In contrast, we find that software overhead on a modern Linux server prevents exploiting the full potential of these high speed storage devices. Native Command Queueing is supported by the core and the performance results highlight its importance in the context of SSDs, especially for small block transfers. The small size of our SATA core (1.5% of the logic resources on a Virtex-6 FPGA) indicates that an on-chip RAID storage system is feasible.

关键词： Field programmable gate arrays Synchronization Registers Linux Protocols Performance evaluation Software

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Teaching FPGA system design via a remote laboratory facility

Teaching FPGA system design via a remote laboratory facility

引用

International Conference on Field Programmable Logic and Applications

作者： Yamuna Rajasekhar William V. Kritikos Andrew G. Schmidt Ron Sass Reconfigurable Computing Systems Laboratory University of North Carolina Charlotte Charlotte NC USA

This short paper describes a remote laboratory facility for platform FPGA education. With the addition of an inexpensive piece of hardware, many commercial off-the-shelf FPGA development boards can be made suitable for use in a remote laboratory. The hardware and software required to implement a remote laboratory has been developed and a remote laboratory facility deployed at the University of North Carolina at Charlotte. Advantages, concerns, and actual costs are reported. The experience of using this facility in a senior/first-year graduate-level platform FPGA course is also described. Although these data are preliminary, survey results and first-hand experience with the laboratory were very encouraging and suggests that further studies on student learning are warranted.

关键词： Field programmable gate arrays Laboratories Software Power capacitors Servers Hardware Education

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Real Time ARM-based Traffic Level of Service Classification System

Real Time ARM-based Traffic Level of Service Classification ...

引用

International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology

作者： Phuc Nguyen The Ngoc Anh Nguyen Hoang Tung Anh Nguyen Them Nguyen Xuan Lam Le Tung Viet-Hoa Do Nam Pham Ngoc Embedded Systems and Reconfigurable Computing Laboratory School of Electronics and Telecommunications Hanoi University of Science and Technology Vietnam

ISBN: (纸本)9781467397506

Traffic Level of Service (LOS) information is crucial for traffic management systems, especially in urban areas. One method to estimate traffic LoS is to use a central server system to process traffic images captured by road side cameras. However, this approach requires a high performance server system as well as high network throughput to transmit images from the cameras to the server, which results in very high system deployment cost. In this paper, we propose a cost effective distributed solution using smart cameras each of which is equipped with a low cost ARM microprocessor to estimate the LOS from the captured traffic images. The LOS of a road estimated by a corresponding camera will then be sent to a traffic information server. In this study, LOS is determined based on the average traffic flow speed and the road occupancy. The Lucas Kanade optical flow method is used to estimate the speed of the traffic flow. In order to have a real time processing on a low cost platform, the whole LOS estimation algorithm has been optimized. The experimental results show that our optimized implementation can process traffic images in real time on an ARM Cortex-A8 platform and is 4 times faster than an OpenCV based implementation on the same platform.

关键词： Level of service (LOS) Image processing Optimization ARM

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Hardware implementation of MPI_Barrier on an FPGA cluster

Hardware implementation of MPI_Barrier on an FPGA cluster

引用

International Conference on Field Programmable Logic and Applications

作者： Shanyuan Gao Andrew G. Schmidt Ron Sass Reconfigurable Computing Systems Laboratory Electrical & Computer Engineering Department North Carolina State University Charlotte USA

Message-Passing is the dominant programming model for distributed memory parallel computers and Message-Passing Interface (MPI) is the standard. Along with point-to-point send and receive message primitives, MPI includes a set of collective communication operations that are used to synchronize and coordinate groups of tasks. The MPI_Barrier, one of the most important collective procedures, has been extensively studied on a variety of architectures over last twenty years. However, a cluster of Platform FPGAs is a new architecture and offers interesting, resource-efficient options for implementing the barrier operation. This paper describes an FPGA implementation of MPI_Barrier. The premise is that barrier (and other collective communication operations) are very sensitive to latency as the number of nodes scales to the tens-of-thousands. The relatively slow processors found on FPGAs will significantly cap performance. The FPGA hardware design implements a tree-based algorithm and is tightly integrated with the custom high-speed on-chip/off-chip network. MPI access is available through a specially-designed kernel module. This effectively offloads the work from the CPU and OS into hardware. The evaluation of this design shows significant performance gains compared with a conventional software implementation on both an FPGA cluster and a commodity cluster. Further, it suggests that moving other MPI collective operations into hardware would be beneficial.

关键词： Hardware Field programmable gate arrays Parallel programming Computer interfaces Concurrent computing Distributed computing Delay Algorithm design and analysis Network-on-a-chip Kernel

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Checkpoint/Restart and Beyond: Resilient High Performance computing with FPGAs

Checkpoint/Restart and Beyond: Resilient High Performance Co...

引用

Annual IEEE Symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Andrew G. Schmidt Bin Huang Ron Sass Matthew French Reconfigurable Computing Systems Laboratory University of North Carolina Charlotte USA Information Sciences Institute University of Southern California USA

As FPGA resources continue to increase, FPGAs present attractive features to the High Performance computing community. These include the power-efficient computation and application-specific acceleration benefits, as well as tighter integration between compute and I/O resources. This paper considers the ability of an FPGA to address another, increasingly important, feature - resiliency. Specifically, a minimally-invasive monitoring infrastructure operating over a sideband network is presented. This includes a multi-chip protocol, IP cores that implement the protocol, and a tool to instrument existing hardware accelerator FPGA designs. To demonstrate the functionality, the system has been implemented on a cluster of FPGA devices running off-the-shelf MPI and Linux. We demonstrate the ability to do integrated software and hardware accelerator check pointing with restart under a variety of injected faults.

关键词： Monitoring Context Hardware Field programmable gate arrays Registers Software Amplitude modulation

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Scalability Studies of the BLASTn Scan and Ungapped Extension Functions

Scalability Studies of the BLASTn Scan and Ungapped Extensio...

引用

International Conference on reconfigurable computing and FPGAs (ReConFig)

作者： Siddhartha Datta Ron Sass Reconfigurable Computing Systems Laboratory Electrical & Computer Engineering Department University of North Carolina Charlotte Charlotte NC USA

BLASTn is a ubiquitous and important tool used for large scale DNA analysis. As such, it is a good candidate for acceleration with FPGAs. The aim of this paper is two-fold. First, building upon our prior BLAST work we describe a design composed of multiple cores that can be scaled in two dimensions. The ungapped extension and a second dimension are new in this work. Second, we use this non-trivial example to explore spatially scalable designs. To provide the ability to move the design to a future generation chip, a mathematical model of performance that incorporates all of the system design parameters and the user's preference (high throughput vs low latency) is developed. We demonstrate here that the model correctly predicts the optimal ratio between the two dimensions on a Xilinx Virtex-4 and measures four to five times faster performance figures as compared to a state of the art general purpose processor.

关键词： Scalability Large-scale systems DNA Acceleration Field programmable gate arrays Buildings Mathematical model Throughput Delay Predictive models

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Merging Programming Models and On-chip Networks to Meet the Programmable and Performance Needs of Multi-core systems on a Programmable Chip

Merging Programming Models and On-chip Networks to Meet the ...

引用

International Conference on reconfigurable computing and FPGAs (ReConFig)

作者： Andrew G. Schmidt William V. Kritikos Erik K. Anderson Ron Sass Matthew French Reconfigurable Computing Systems Laboratory University of North Carolina Charlotte USA Information Science Institute University of Southern California USA

The reconfigurable Data-Stream Hardware Software Architecture (Redsharc) is a programming model and network-on-a-chip solution designed to scale to meet the performance needs of multi-core systems on a programmable chip. Redsharc uses an abstract API that allows programmers to develop systems of simultaneously executing kernels, in software or hardware, that communicate over a seamless interface. To support high performance systems with numerous hardware kernels, Redsharc incorporates two on-chip networks that directly mimic the API. Our results show that Redsharc running at 200 MHz, 32-bit data widths can achieve 800 MBps per stream from hardware to hardware, 480 MBps for a software to hardware stream, and between 20 MBps and 400 MBps for random access data in blocks, regardless of the number of kernels in the system.

关键词： Kernel Hardware Switches Field programmable gate arrays System-on-a-chip Program processors

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Improving FPGA Design and Evaluation Productivity with a Hardware Performance Monitoring Infrastructure

Improving FPGA Design and Evaluation Productivity with a Har...

引用

International Conference on reconfigurable computing and FPGAs (ReConFig)

作者： Andrew G. Schmidt Ron Sass Information Sciences Institute University of Southern California USA Reconfigurable Computing Systems Laboratory University of North Carolina Charlotte USA

Hardware design with FPGAs can be a daunting task, even for experienced engineers. Even with sophisticated tools and improvements in high-level language to gates approaches, an engineer can expend significant effort simply implementing the design. Often, when the design is evaluated on the FPGA, the performance may not be what was expected. As a result, an engineer may go back and augment the design to include performance monitors to help identify the bottlenecks in the system or to aid in the debugging of the design. This work aims to alleviate this effort. We present the Hardware Performance Monitoring Infrastructure (HwPMI), which includes a collection of software tools and hardware cores that can be used to profile the current design, recommend/insert performance monitors directly into the HDL, and retrieve the monitored data with minimal invasion to the design. This paper reports on the functionality of the tools and the integration of the hardware cores into existing designs.

关键词： Monitoring Hardware Field programmable gate arrays Hardware design languages Registers Program processors

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