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Design of a scalable digital Wireless Channel Emulator for networking radios

Design of a scalable digital Wireless Channel Emulator for n...

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MILCOM, Military Communications Conference

作者： Scott Buscemi Ron Sass Advanced Communication Technologies Laboratory SPAWAR Systems Center Atlantic Charleston SC USA Reconfigurable Computing Systems Laboratory University of North Carolina at Charlotte Charlotte NC USA

The utilization of digital Wireless Channel Emulators (WCE) with networking radios is hampered by the inability to efficiently scale a digital WCE to a large number of nodes. While analog WCEs are capable of large numbers of nodes they cannot cost effectively emulate channel effects such as fading and multipath which significantly limits the accuracy and flexibility of the emulation. If such a large scale digital WCE were to exist, a significant amount of time and money could be saved by testing networking radios in a laboratory before running lengthily and costly field tests. By utilizing the repeatability of a laboratory environment it will be possible to investigate and solve issues more quickly and efficiently. This will enable the performance of the radios to be known with a high degree of certainty before they are brought to the field. This paper describes research into scalability of digital wireless channel emulators highlighting technical challenges and presents a design solution that will meet the needs of current and future networking radio system testing. The major design challenges of the system include: computational and network capability, end-to-end propagation delay, and accuracy of the emulation. A solution to these issues involves the creation of an FPGA computational cluster networked via high speed transceivers and a signal path design that utilizes hardware resources effectively. A prototype was developed using this signal path design and COTS hardware to explore each of the challenges and to take metrics demonstrating the capability of a full scale system to meet these challenges. Additionally, this prototype was connected to Joint Tactical Radio systems (JTRS) radios to demonstrate the capabilities of the system with military hardware.

关键词： Field programmable gate arrays Delay Hardware Prototypes Bandwidth Equations Clocks

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Design and utilization of an FPGA cluster to implement a Digital Wireless Channel Emulator

Design and utilization of an FPGA cluster to implement a Dig...

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International Conference on Field Programmable Logic and Applications

A Digital Wireless Channel Emulator (DWCE) is a system that is capable of emulating the RF environment for a group of radios. A major issue with current designs is that they do not scale to a large enough number of nodes to emulate meaningful network due to the amount of computations required for such a system. This paper proposes a novel DWCE design based on a cluster of FPGA devices. By decentralizing the signal processing it is possible to increase the available computational resources to the point where they are no longer the limiting factor to scalability. It demonstrates feasibility by analyzing the computational and network requirements of the application and showing how the proposed design meets those needs. The paper also describes the physical design of a new 64 node FPGA cluster that is being manufactured. An implementation on prototype nodes of this cluster demonstrates the machine will support a high fidelity emulation for 32 radios or a lower-fidelity emulation for 128 radios.

关键词： Field programmable gate arrays Wireless communication Mathematical model Equations Emulation Radio frequency Graphics processing unit

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Characterizing Effective Memory Bandwidth of Designs with Concurrent High-Performance computing Cores

Characterizing Effective Memory Bandwidth of Designs with Co...

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International Conference on Field Programmable Logic and Applications

作者： Andrew G. Schmidt Ron Sass Ittc University of Kansas Lawrence KS USA Reconfigurable Computing Systems Laboratory University of North Carolina Charlotte Charlotte NC USA

In this paper we investigate several common bus architectures and measure effective bandwidth between High Performance computing cores and off-chip memory. Contributions of this paper include (i) characterizing the behavior of four common organizations using off-the-shelf IP cores, (ii) an investigation of the effect of multiple computational cores sharing the bus structures, and (iii) the development of a testing methodology which simulates different access patterns and accurately measures bandwidth. The results show that while some bus architectures arc clearly belter than others, none approach the theoretical bandwidth of the memory interface. Furthermore, negotiating the bus protocol is a significant source of overhead. So much so that it effectively hides any performance one might gain from trying to access the off-chip DRAMs using an "intelligent" access pattern.

关键词： Bandwidth Concurrent computing Field programmable gate arrays Computer architecture Embedded computing reconfigurable logic Testing Computational modeling Access protocols Performance gain

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Low-Latency FPGA Based Financial Data Feed Handler

Low-Latency FPGA Based Financial Data Feed Handler

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Annual IEEE Symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Robin Pottathuparambil Jack Coyne Jeffrey Allred William Lynch Vincent Natoli Reconfigurable Computing Systems Laboratory University of North Carolina Charlotte Charlotte NC USA Stone Ridge Technology Bel Air MD USA

Financial exchanges provide real time data feeds containing trade, order and status information to brokers, traders and other market makers. ITCH is one such market data feed that is disseminated by the NASDAQ exchange. The work presented in this paper describes an FPGA based ITCH feed handler and processing system. The handler, built on the Stone Ridge RDX-11 hardware platform with a combination of HDL and Impulse C, accepts and processes ITCH packet sat line speed with extremely low latency. Our implementation parses sixteen different stock symbols in the feed and generates an outbound packet on the NASDAQ one second heartbeat. The unit was tested with an artificial feed that could be adjusted in speed to simulate market surges. The system demonstrated a turnaround latency of 2.7μs with very little variation for all tested feed rates. The CPU equivalent demonstrated 38±22μs(1x rate) with a long tail illustrating the variability inherent to processing by the host O/S. The FPGA solution demonstrated ultra-low, deterministic latency and was able to continue processing data at the line rate limit.

关键词： Feeds Field programmable gate arrays Bridges Hardware Monitoring Algorithm design and analysis Generators

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Harnessing Unreliable Cores in Heterogeneous Architecture: The PyDac Programming Model and Runtime

Harnessing Unreliable Cores in Heterogeneous Architecture: T...

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International Conference on Dependable systems and Networks (DSN)

作者： Bin Huang Ron Sass Nathan Debardeleben Sean Blanchard Reconfigurable Computing Systems Laboratory University of North Carolina at Charlotte Charlotte North Carolina USA Ultrascale Systems Research Center Los Alamos National Laboratory Los Alamos NM USA

Heterogeneous many-core architectures combined with scratch-pad memories are attractive because they promise better energy efficiency than conventional architectures and a good balance between single-thread performance and multi-thread throughput. However, programmers will need an environment for finding and managing the large degree of parallelism, locality, and system resilience. We propose a Python-based task parallel programming model called PyDac to support these objectives. PyDac provides a two-level programming model based on the divide-and-conquer strategy. The PyDac runtime system allows threads to be run on unreliable hardware by dynamically checking the results without involvement from the programmer. To test this programming model and runtime, an unconventional heterogeneous architecture consisting of PowerPC and ARM cores was developed and emulated on an FPGA device. We inject faults during the execution of micro-benchmarks and show that through the use of double and triple modular redundancy we are able to complete the benchmarks with the correct results while only incurring a proportional performance penalty.

关键词： Runtime Programming Computer architecture Redundancy Resilience Hardware

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Volcan: System Integration of HLS and HMC on FPGAs

Volcan: System Integration of HLS and HMC on FPGAs

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International Conference on reconfigurable computing and FPGAs (ReConFig)

作者： Abhi D. Rajagopala Ron Sass Andrew G. Schmidt Reconfigurable Computing Systems Laboratory University of North Carolina at Charlotte Charlotte NC USA Information Sciences Institute University of Southern California Arlington VA USA

ISBN: (纸本)9781728119588

High-Level Synthesis (HLS) is a process that translates traditional software languages (C/C++/Java) into either a hardware description language representation or a netlist representation that, ultimately, can be implemented on an FPGA device, for example. The original goal was to make advanced computing accelerators accessible to embedded computing systems programmers. However, the technology has attracted the interest of high-performance computing (HPC) programmers as well. This would be a huge benefit because labor statistics suggest that every year 10x as many software programmers graduate for every hardware designer [1]. However, HPC programmers use large in-core datasets versus the transient, streaming data sets that are common in embedded systems. Looking forward, it is appropriate to explore the behavior of HLS with next-generation memory technologies, like the Hybrid Memory Cube (HMC).

关键词： embedded systems field programmable gate arrays hardware description languages parallel processing Field programmable gate arrays Hardware design languages hue lightness saturation Embedded systems PARALLEL PROCESSING (COMPUTERS) hardware motion compensation Computer personnel High Performance computing Embedded computing systems Integration

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Towards a hardware fault-injection testbed to support reproducible resiliency experiments

Towards a hardware fault-injection testbed to support reprod...

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2009 Workshop on Resiliency in High Performance, Resilience'09, Co-located with the 2009 International Symposium on High Performance Distributed computing Conference, HPDC'09

作者： Sass, Ron Sharma, Rahul R. DeBardeleben, Nathan Reconfigurable Computing Systems Lab. Univ. of N. Carolina at Charlotte 9201 University City Blvd. Charlotte NC 28223 United States Los Alamos National Laboratory MS B272 P. O. Box 1663 Los Alamos NM 87544 United States

ISBN: (纸本)9781605585932

As the largest computers in world continue to scale up to very large number of nodes, significant new problems emerge. Due to a number of different sources, hard and soft failures cause correctness issues and performance degradation in high component count machines. These issues simply do not occur at an appreciable rate in smaller scale machines. This presents a serious problem to researchers interested in studying and countering the issues because effects are not reproducible smaller scale testbeds. The reconfigurable computing Cluster (RCC) project is investigating the feasibility of using just FPGAs accelerators to build a high end computing computing system. However, since the hardware is very configurable, it is possible to also use this infrastructure to introduce special-purpose hardware cores that are designed to perturb or corrupt an existing system in a controlled way. This architecture offers an ideal platform for performing fault injections and "Heisenberg-free" monitoring of parallel programs. This work-in-progress describes several potential fault injectors and system monitors. A "bus cycle stealer" is demonstrated. This small hardware core can be programmed to wake up periodically and execute a variable number bus transactions. The effect on performance (single node and 16 node systems) are reported. Copyright 2009 ACM.

关键词： Field programmable gate arrays (FPGA)

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A Smart-NIC-Based Power-Proxy Solution for Reduced Power Consumption during Instant Messaging

A Smart-NIC-Based Power-Proxy Solution for Reduced Power Con...

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IEEE Green Technologies Conference (IEEE-Green)

作者： Dexiang Wang Janise McNair Alan George Wireless and Mobile Systems Laboratory Department of Electrical and Computer Engineering University of Florida Gainesville USA NSF Center for High-Performance Reconfigurable Computing (CHREC) Department of Electrical and Computer Engineering University of Florida Gainesville USA

ISBN: (纸本)9781424452743

The major challenge to achieving efficient power management for local computers that serve as edge devices of the Internet is to achieve long sleeping times while at the same time maintaining network connectivity. By modifying the network interface card (NIC) with a low-weight proxy module that can handle a certain amount of network protocol semantics and hence still keep the local computer alive on the Internet, a longer host sleeping time can be achieved, while keeping many of the components, including CPU, memory, motherboard, hard drive, etc, remain in a very-low-energy mode. In this paper, we pursue a power-proxy solution to the widely-used Instant Messenger (IM) applications. Yahoo! ® Messenger is selected for a case study to investigate its communication protocol YMSG. Furthermore, the decision on inactivity time-out values is a crucial factor for energy savings, but the random nature of idle periods makes the decision another challenge. We formulate the decision problem into a stochastic program and propose an adaptive algorithm to set up appropriate inactivity time-out values. Simulations show that the proposed power-proxy solution combined with the inactivity time-out setup algorithm can efficiently reduce the power consumption of an edge computer.

关键词： Energy consumption Computer networks IP networks Protocols Computer network management Energy management Network interfaces Computer interfaces Central Processing Unit Drives

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Noise impact of single-event upsets on an FPGA-based digital filter

Noise impact of single-event upsets on an FPGA-based digital...

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International Conference on Field Programmable Logic and Applications

作者： Brian H. Pratt Michael J. Wirthlin Michael Caffrey Paul Graham Keith Morgan NSF Center of High Performance Reconfigurable Computing (CHREC) Department of Elec. & Comp. Engineering Brigham Young University Provo UT USA ISR-3 Space Data Systems Los Alamos National Laboratory Los Alamos NM USA

Field-programmable gate arrays are well-suited to DSP and digital communications applications. SRAM-based FPGAs, however, are susceptible to radiation-induced single-event upsets (SEUs) when deployed in space environments. These effects are often handled with the area and power-intensive TMR mitigation technique. This paper evaluates the effects of SEUs in the FPGA configuration memory as noise in a digital filter, showing that many SEUs in a digital communications system cause effects that could be considered noise rather than circuit failure. Since DSP and digital communications applications are designed to withstand certain types of noise, SEU mitigation techniques that are less costly than TMR may be applicable. This could result in large savings in area and power when implementing a reliable system. Our experiments show that, of the SEUs that affected the digital filter with a 20 dB SNR input signal, less than 14% caused an SNR loss of more than 1 dB at the output.

关键词： Digital filters Single event transient Working environment noise Field programmable gate arrays Digital communication Circuit noise Digital signal processing Power system reliability Single event upset Signal to noise ratio

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Topology design and performance analysis for networked earth observing small satellites

Topology design and performance analysis for networked earth...

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MILCOM, Military Communications Conference

作者： Paul Muri Janise McNair Joe Antoon Ann Gordon-Ross Kathryn Cason Norman Fitz-Coy Wireless and Mobile (WAM) Systems Laboratory Department of Electrical and Computer Engineering University of Florida Gainesville FL USA NSF Center of High Performance Reconfigurable Computing (CHREC) Department of Electrical and Computer Engineering University of Florida Gainesville FL USA Space Systems Group (SSG) Department of Mechanical and AeroSpace Engineering University of Florida Gainesville FL USA

In order to network small satellite constellations for Earth observation and communication, several limitations must be addressed, including distributed topology management, slow down-link data-rates, and single point-to-point communication. Since distributed satellite constellations exacerbate the severity of these limitations, thorough analysis of a constellation's network performance is required to ensure that task objectives are achievable. In this paper, we designed network topologies using Satellite Toolkit (STK) for two low Earth orbit (LEO) Earth observing small satellite constellations: a sun-synchronous repeating ground track constellation and a flower (an elliptical repeating ground track) constellation. Both constellations include six sink satellites that provide a high speed down-link relay point to a ground station. We compared the constellations' inter-satellite links and down-links with respect to network metrics including access window time, drop-ratio, and throughput. We evaluated these network metrics using the Network Simulator (ns-2). Though previous works have proposed sun-synchronous and flower small satellite constellations for Earth observation, these constellations have not been analyzed for these network metrics. Results show that the sun-synchronous constellation with a repeating ground track outperforms the flower constellation with respect to more access time, lower drop-ratio, and higher throughput. Additionally, our simulations determined the optimum media access control slot time and packet transmission intervals for long distance satellite links. Further, our method of designing satellite constellation topologies in STK and exporting them to ns-2 can be used for future studies on any desired constellation network performance evaluations.

关键词： Satellites Satellite broadcasting Orbits Earth Satellite constellations Databases Mobile communication

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