检索结果-内蒙古大学图书馆

IEEE International Conference on Robotics and Automation (ICRA)

作者： K.G. Shin Q. Zheng Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The problem of scheduling job operations in an automatic assembly line used for manufacturing a small to medium volume of mixed workparts is addressed. The assembly line model differs from the classical flow shop model in the following three aspects: (1) there are no buffers at machine stations, (2) constraints associated with the material transport system are included, and (3) for each batch production, workparts are distinguished in groups, rather than individually. An optimal algorithm that requires very little computation is derived by minimizing the total finish time for two machine assembly lines. This result is generalized to the problem of scheduling an assembly line with m>2 machines processing single-operation jobs. In order to reduce the computational complexity of the latter problem, heuristic algorithms are also proposed and shown to work quite well for all the cases considered. The solution to the problem of scheduling an assembly line with m>2 machines processing multioperation jobs is discussed.< >

关键词： Assembly Job shop scheduling Processor scheduling Pulp manufacturing Flexible manufacturing systems Optimal scheduling Manufacturing automation Heuristic algorithms Scheduling algorithm Laboratories

来源：评论

学校读者我要写书评

暂无评论

Optimal multiple syndrome probabilistic diagnosis

Optimal multiple syndrome probabilistic diagnosis

引用

International Symposium on Fault-Tolerant computing (FTCS)

作者： S. Lee K.G. Shin Department of Electrical Engineering University of Delaware Newark DE USA Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The authors discuss the distributed self-diagnosis of a multiprocessor/multicomputer system based on interprocessor tests with imperfect fault coverage (thus also permitting intermittently fault processors). It is shown that by using multiple fault syndromes, it is possible to achieve significantly better diagnosis than by using a single fault syndrome, even when the amount of time devoted to testing is the same. The authors derive a multiple syndrome diagnosis algorithm that is optimal in the level of diagnostic accuracy achieved (among diagnosis algorithms of a certain type to be defined) and produces good results even with sparse interconnection networks and interprocessor test with low fault coverage. Furthermore, they prove upper and lower bounds are proved on the number of fault syndromes required to produce asymptotically a 100% correct diagnostic as N to infinity . Their solution and another multiple syndrome diagnosis solution by D. Fussell and S. Rangarajan are evaluated both analytically and with simulations.< >

关键词： Fault diagnosis System testing Upper bound Multiprocessing systems Automatic testing Multiprocessor interconnection networks Analytical models Algorithm design and analysis H infinity control Laboratories

来源：评论

学校读者我要写书评

暂无评论

A Bayesian approach to fault classification 90

A Bayesian approach to fault classification

引用

Proceedings of the 1990 ACM SIGMETRICS conference on Measurement and modeling of computer systems

作者： Tein-Hsiang Lin Kang G. Shin Department of Electrical and Computer Engineering State University of New York at Buffalo Buffalo New York Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science The University of Michigan Ann Arbor Michigan

ISBN: (纸本)9780897913591

According to their temporal behavior, faults in computer systems are classified into permanent, intermittent, and transient faults. Since it is impossible to identify the type of a fault upon its first detection, the common practice is to retry the failed instruction one or more times and then use other fault recovery methods, such as rollback or restart, if the retry is not successful. To determine an “optimal” (in some sense) number of retries, we need to know several fault parameters, which can be estimated only after classifying all the faults detected in the *** this paper we propose a new fault classification scheme which assigns a fault type to each detected fault based on its detection time, the outcome of retry, and its detection symptom. This classification procedure utilizes the Bayesian decision theory to sequentially update the estimation of fault parameters whenever a detected fault is classified. An important advantage of this classification is the early identification of presence of an intermittent fault so that appropriate measures can be taken before it causes a serious damage to the system. To assess the goodness of the proposed scheme, the probability of incorrect classification is also analyzed and compared with simulation results.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Monotonicity and Maximal Solution of Generalized Algebraic Riccati Equations

Monotonicity and Maximal Solution of Generalized Algebraic R...

引用

American Control Conference (ACC)

作者： Carlos E. de Souza Marcelo D. Fragoso Department of Electrical Engineering and Computer Science University of Newcastle NSW Australia National Laboratory for Scientific Computing Department of Research and Development LNCC/CNPq Rio de Janeiro Brazil

Monotonicity and existence of maximal solution is proved for a generalized version of the well-known standard algebraic Riccati equations which arise in certain stochastic optimal control problems.

关键词： Riccati equations Symmetric matrices Optimal control Eigenvalues and eigenfunctions Difference equations Cost function Laboratories Scientific computing Research and development Standards development

来源：评论

学校读者我要写书评

暂无评论

Automatic classification of node types in switch-level descriptions

Automatic classification of node types in switch-level descr...

引用

IEEE International Conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： D.T. Blaauw P. Banerjee J.A. Abraham Center for Reliable an High Performance Computing Coordinated Science Laboratory University of Illinois Urbana-Champaign Urbana IL USA Department of Electrical & Computer Engineering University of Texas Austin Austin TX USA

In switch-level simulation, nodes carry a charge on their parasitic capacitance from one evaluation to the next, which gives them a memory quality. A node is classified as temporary if its memory aspect is lost and cannot affect the circuit operation, whereas a node is classified as a memory node if the memory of the node is maintained and can affect the circuit operation. Accurate classification of nodes into temporary and memory nodes increases the performance of compiled simulators and high-level model generators. An approach for reliable automatic classification of nodes in a switch-level description is introduced. Both an exhaustive, exponential-time algorithm and a polynomial-time heuristic are presented. The heuristic was implemented and tested for several large circuits, including a commercial microprocessor. For this processor, the proposed heuristics identified an average of 92% of all nodes as temporary nodes. The heuristic was applied in a high-level model generator and significantly increased its performance.< >

关键词： Circuit simulation Parasitic capacitance Circuit testing Maintenance Polynomials Switching circuits Switched capacitor circuits Joining processes Capacitance measurement Size measurement

来源：评论

学校读者我要写书评

暂无评论

THE COMMAND SUPPORT AT-SEA EXPERIMENT

引用

NAVAL ENGINEERS JOURNAL 1990年第3期102卷 25-36页

作者： BUSCHER, DJ SUNDAY, DM David J. Buscher:is an electrical engineer on the Principal Professional Staff of the Fleet Systems Department of The Johns Hopkins University Applied Physics Laboratory. He earned his BS degree in electrical engineering from Villanova University in 1967 an MSEE degree from the University of Maryland in 1972 and an MS degree in technical management from The Johns Hopkins University in 1985. He was the lead engineer on the Command Support At-Sea Experiment Project. He started his career in 1967 with the U.S. Army Harry Diamond Laboratory working on computer and communications projects. During this time he worked in Vietnam with the United States Army Vietnam Science Advisor Office. Since joining JHU/APL in 1978 he has worked on a variety of projects associated with computer graphics hospital patient information systems computer networks autonomous underwater vehicles and satellite communications. He is currently assistant group supervisor of the Computer Systems Group. Daniel M. Sunday:is a mathematician on the Principal Professional Staff of the Fleet Systems Department of The Johns Hopkins University Applied Physics Laboratory. He earned his Ph.D. in mathematics from the University of Minnesota in 1971 and did postdoctoral research on neural networks at the University of California at Berkeley. Since joining JHU/APL in 1980 Dr. Sunday has worked as a designer and developer of software systems with emphasis on medical imaging interactive graphics natural language interfaces and software standards. He was the network designer for the Headquarters Integrated Office System (HIOS) Network for the Army at the Pentagon. He is currently the lead software engineer on the Command Support At-Sea Experiment Project.

The Command Support At-Sea Experiment (CS@SE) provides experimental advanced graphics display systems consisting of large screen color displays and operator console color displays in the combat information center (CIC) of an Aegis cruiser and in the tactical flag command center (TFCC) of an aircraft carrier. CS@SE systems are designed to prototype potential command support capabilities in an at-sea environment to validate and refine requirements for planned production system upgrades. These systems use sophisticated color graphics techniques to provide real-time tactical displays that improve the availability of information to an operator by reducing clutter through the use of color, area fill, transparen overlays and intensity coding of track symbols. Interfaces wen developed with the Aegis Display System (ADS), Shipboarc Gridlock System with Auto-correlation (SGS/AC), Flag Dats Display System (FDDS) and Tomahawk Engagement Planning and Exercise Evaluation System (TEPEE) that provided the data for the presentation of a tactical display. Display elements included both real-time and over-the-horizon (OTH) surface track data, velocity leaders, tags, uncertainty ellipses, and history trails. The display also included filled land masses, country boundaries, commercial airways, cities, graphics overlays (i.e., operational areas), weapon system missile performance contours, and engagement plans. This paper describes the experiment, its installation and integration into the shipboard environments of an Aegis cruiser (USS Leyte Gulf ) and an aircraft carrier (USS America , its usage by the ships companies and embarked staffs, and the experiment result! and findings. Key conclusions of the experiment are: 1 Advanced graphics color displays can significantly enhance the ability of the warfighter to assimilate a complex tactical display. 2 Both ships reported a requirement for a correlated OTH and real-time track display with the ability to clearly differentiate the two types

关键词： computer Graphics

来源：评论

学校读者我要写书评

暂无评论

Message routing in HARTS with faulty components

Message routing in HARTS with faulty components

引用

International Symposium on Fault-Tolerant computing (FTCS)

作者： A. Olson K.G. Shin Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The authors develop a routing scheme in two steps for a wrapped hexagonal mesh, called HARTS (hexagonal architecture for real-time systems), which ensures the delivery of every message as long as there is a path between its source and destination. The scheme can also detect the nonexistence of a path between a pair of nodes in a finite amount of time. Moreover, the scheme requires each node in HARTS to know only the state (faulty or not) of each of its own links. The performance of the simple routing scheme is simulated for three- and five-dimensional H-meshes while the physical distribution of faulty components is varied. It is shown that a shortest path between the source and the destination of each message is taken with a high probability, and a path, if one exists, is usually found very quickly.< >

关键词： Routing Laboratories Fault tolerant systems Computational modeling Distributed computing Parallel processing Hypercubes Broadcasting NASA Contracts

来源：评论

学校读者我要写书评

暂无评论

Minimum time trajectory planning for dual robot systems

Minimum time trajectory planning for dual robot systems

引用

IEEE Conference on Decision and Control

作者： K.G. Shin Q. Zheng Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The problem of planning minimum time collision-free trajectories for a dual robot system is addressed. It is shown that this problem can be solved by first planning the minimum time trajectory for each robot without considering the existence of the other and then combining the two individual trajectories. This combination is accomplished by delaying one of the two trajectories in such a way that the time required for the coordinated motion of the two robots is minimized while avoiding collision between them. The optimality of the method is rigorously proved, the practical aspects of its realization are discussed, and example is presented.< >

关键词： Trajectory Robot kinematics Path planning Robot sensing systems Motion planning Laboratories computer science Delay effects Artificial intelligence Productivity

来源：评论

学校读者我要写书评

暂无评论

A module-sliced approach for high yield VLSI/WSI processors

A module-sliced approach for high yield VLSI/WSI processors

引用

IEEE International Conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： Y.-C. Chang K.G. Shin Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The module-sliced approach is realized in a reconfigurable fault-tolerant segmented array processor (RFTSAP). The basic building block of RFTSAP is a node which consists of a processor, local memory, and a programmable I/O unit (PIOU). The PIOU allows any group of processors to be combined to perform the functions of a large processor module. The yield of a large processor module can be improved 2 to 4 times compared to that of approaches not using the module-sliced method.< >

关键词： Very large scale integration Switches Microprocessors Fault tolerance Registers Strontium Laboratories redundancy Process control computer architecture

来源：评论

学校读者我要写书评

暂无评论

An efficient design of embedded memories and their testability analysis using Markov chains

An efficient design of embedded memories and their testabili...

引用

International Conference on Wafer Scale Integration

作者： P. Mazumder Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

A design strategy for efficient and comprehensive random testing of embedded random-access memory (RAM), where the address, read/write, and data input lines are not directly controllable and the data output lines are not externally observable, is presented. Unlike conventional approaches which use a linear feedback shift register (LFSR) to generate a signature and a register to store the reference fault-free signature, this technique uses a testable design which both accelerates the test by a factor of 0.5 square root n in an n-bit RAM and improves the test reliability by eliminating the LFSR. The problem of memory initialization has been elegantly circumvented by using word-line flag registers. An in-depth and comprehensive analysis of the functional faults, such as stuck-at, coupling, and pattern-sensitive, is performed. The analysis shows that, in order to test a 1-Mb RAM for common functional faults, the technique needs only 1 s, as opposed to about an hour needed by the conventional random testing.< >

关键词： Random access memory Circuit testing Read-write memory Circuit faults Registers Built-in self-test Life estimation Vectors Gold Sequential analysis

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：