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Synthesizing service Composition Models on the Basis of Temporal Business Rules

Journal of Computer Science & Technology 2008年第6期23卷 885-894页

作者：喻坚韩燕波韩军金岩 Paolo Falcarin Maurizio Morisio Department of Automation and Information Politecnico di Torino School of Computer Science The University of Adelaide Grid and Service Computing Research Center Institute of Computing TechnologyChinese Academy of Sciences Faculty of ICT Swinburne University of Technology

Transformational approaches to generating design and implementation models from requirements can bring effectiveness and quality to software development. In this paper we present a framework and associated techniques to generate the process model of a service composition from a set of temporal business rules. Dedicated techniques including path- finding, branching structure identification and parallel structure identification are used for semi-automatically synthesizing the process model from the semantics-equivalent Finite State Automata of the rules. These process models naturally satisfy the prescribed behavioral constraints of the rules. With the domain knowledge encoded in the temporal business rules, an executable service composition program, e.g., a BPEL program, can be further generated from the process models. A running example in the e-business domain is used for illustrating our approach throughout this paper.

关键词： service composition composition synthesis behavioral model temporal patterns

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Efficient FPGA-based graph processing with hybrid pull-push computational model

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Frontiers of Computer Science 2020年第4期14卷 13-28页

作者： Chengbo YANG Long ZHENG Chuangyi GUI Hai JIN National Engineering Research Center for Big Data Technology and System/Service Computing Technology and System Lab/Cluster and Grid Computing Lab School of Computer Science and TechnologyHuazhong University of Science and TechnologyWuhan430074China

Hybrid pull-push computational model can provide compelling results over either of single one for processing real-world *** and pipeline parallelism of FPGAs make it potential to process different stages of graph ***,considering the limited on-chip resources and streamline pipeline computation,the efficiency of hybrid model on FPGAs often suffers due to well-known random access feature of graph *** this paper,we present a hybrid graph processing system on FPGAs,which can achieve the best of both *** approach on FPGAs is unique and novel as ***,we propose to use edge block(consisting of edges with the same destination vertex set),which allows to sequentially access edges at block granularity for locality while still preserving the *** to the independence of blocks in the sense that all edges in an inactive block are associated with inactive vertices,this also enables to skip invalid blocks for reducing redundant ***,we consider a large number of vertices and their associated edge-blocks to maintain a predictable execution *** also present to switch models in advance with few stalls using their state *** evaluation on a wide variety of graph algorithms for many real-world graphs shows that our approach achieves up to 3.69x speedup over state-of-the-art FPGA-based graph processing systems.

关键词： graph processing efficiency computational model FPGAs

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BEAP： An End-User Agile Programming Paradigm for Business Applications

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Journal of Computer Science & Technology 2006年第4期21卷 609-619页

作者：舒承椿余海燕刘昊植 Research Center for Grid and Service Computing Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 P.R. China Graduate University of the Chinese Academy of Sciences Beijing 100039 P.R. China

Business applications are subject to changes with technology trends or market demands. However, quick response to these changes is still a challenging issue. Most of the existing architectures （e.g., CORBA, Web services） still expose the developers to excessive low-level details and force a tight coupling between program modules. For end users, developing, customizing, and reengineering applications remain difficult and time-consuming tasks. A high-level programming model is presented, together with a descriptive programming paradigm called BEAP, to facilitate end-user programming. In this approach, applications could be visually composed from well-defined software components called ＂funnels＂ in an event-driven fashion. Application examples have shown that, by raising the level of abstraction as well as simplifying the programming model, BEAP could empower end users to build business applications on demand with improved productivity.

关键词： visual programming event-based virtualization component agile pi-calculus

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GraSU: A fast graph update library for fpga-based dynamic graph processing 21

GraSU: A fast graph update library for fpga-based dynamic gr...

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2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2021

作者： Wang, Qinggang Zheng, Long Huang, Yu Yao, Pengcheng Gui, Chuangyi Liao, Xiaofei Jin, Hai Jiang, Wenbin Mao, Fubing National Engineering Research Center for Big Data Technology and System Service Computing Technology and System Lab Cluster and Grid Computing Lab Huazhong University of Science and Technology China

ISBN: (纸本)9781450382182

Existing FPGA-based graph accelerators, typically designed for static graphs, rarely handle dynamic graphs that often involve substantial graph updates (e.g., edge/node insertion and deletion) over time. In this paper, we aim to fill this gap. The key innovation of this work is to build an FPGA-based dynamic graph accelerator easily from any off-the-shelf static graph accelerator with minimal hardware engineering efforts (rather than from scratch). We observe\em spatial similarity of dynamic graph updates in the sense that most of graph updates get involved with only a small fraction of vertices. We therefore propose an FPGA library, called GraSU, to exploit spatial similarity for fast graph updates. GraSU uses a differential data management, which retains the high-value data (that will be frequently accessed) in the specialized on-chip UltraRAM while the overwhelming majority of low-value ones reside in the off-chip memory. Thus, GraSU can transform most of off-chip communications arising in dynamic graph updates into fast on-chip memory accesses. Our experiences show that GraSU can be easily integrated into existing state-of-the-art static graph accelerators with only 11 lines of code modifications. Our implementation atop AccuGraph using a Xilinx Alveo#8482;\U250 board outperforms two state-of-the-art CPU-based dynamic graph systems, Stinger and Aspen, by an average of 34.24× and 4.42× in terms of update throughput, improving further overall efficiency by 9.80× and 3.07× on average. © 2021 ACM.

关键词： Field programmable gate arrays (FPGA)

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A login shell for computing grid

A login shell for computing grid

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4th IEEE International Conference on eScience, eScience 2008

作者： Wang, Xiaoning Lin, Jian Zou, Yongqiang Zha, Li Research Center for Grid and Service Computing Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate School of the Chinese Academy of Sciences Beijing 100039 China

ISBN: (纸本)9780769535357

Shell is a most important user interface for HPC users in scientific computing. This paper presents a login shell for computing grid, called GShell, which provides an integrated and uniform environment for constructing, running and managing grid applications. Besides conventional functionality of shell, GShell provides grid-level functionality including grid context maintenance, grid application management interfaces, and extended pipe and redirection semantics. grid contexts avoid repeat information input when a grid application is started. All the grid applications started in GShell are managed in the grid system, and they can be monitored or stopped in a global scope. Extended shell scripts allow constructing new grid applications using existing tools. At present, GShell has been implemented and applied in the CNgrid project, and is proved to be a simple and flexible command-line tool for most scientists to work in the grid. © 2008 IEEE.

关键词： User interfaces

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Correcting Pronoun Homophones with Subtle Semantics in Chinese Speech Recognition 30

Correcting Pronoun Homophones with Subtle Semantics in Chine...

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Joint 30th International Conference on Computational Linguistics and 14th International Conference on Language Resources and Evaluation, LREC-COLING 2024

作者： Zhang, Zhaobo Gan, Rui Yuan, Pingpeng Jin, Hai National Engineering Research Center for Big Data Technology and System Service Computing Technology and System Laboratory Cluster and Grid Computing Laboratory Huazhong University of Science and Technology Wuhan China

ISBN: (纸本)9782493814104

Speech recognition is becoming prevalent in daily life. However, due to the similar semantic context of the entities and the overlap of Chinese pronunciation, the pronoun homophone, especially "他/她/它 (he/she/it)", (their pronunciation is "Tā") is usually recognized incorrectly. It poses a challenge to automatically correct them during the post-processing of Chinese speech recognition. In this paper, we propose three models to address the common confusion issues in this domain, tailored to various application scenarios. We implement the language model, the LSTM model with semantic features, and the rule-based assisted Ngram model, enabling our models to adapt to a wide range of requirements, from high-precision to low-resource offline devices. The extensive experiments show that our models achieve the highest recognition rate for "Tā" correction with improvements from 70% in the popular voice input methods up to 90%. Further ablation analysis underscores the effectiveness of our models in enhancing recognition accuracy. Therefore, our models improve the overall experience of Chinese speech recognition of "Tā" and reduce the burden of manual transcription corrections. © 2024 ELRA Language Resource Association: CC BY-NC 4.0.

关键词： Speech recognition

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A Spreadsheet-like Construct for Streamlining and Reusing Mashups

A Spreadsheet-like Construct for Streamlining and Reusing Ma...

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The 9th International Conference for Young Computer Scientists(第九届国际青年计算机大会)

作者： Yanbo Han Guiling Wang Shaohua Yang Research Center for Grid and Service Computing Institute of Computing Technology Chinese Academy o Research Center for Grid and Service Computing Institute of Computing Technology Chinese Academy o

It is challenging to provide end users an easy-to-use problem-solving tool to combine data from different sources and reuse the results. Inspired by spreadsheets, we argue that spreadsheet-like programming paradigm can help to reduce the complexity and to improve user experience in building mashups. In this paper, we propose a spreadsheet-like construct as the basis of this mashup building paradigm. The construct includes a data model, a ?°nested table?± view structure and a set of carefully chosen mashup operators. Data from a variety of sources is structured like a spreadsheet, and end-users are not necessarily aware of the underlining data flow. SpiderCharlotte, a tool to help end users to build situational applications for their daily uses, was developed to demonstrate the characteristics of this construct.

关键词： Situational applications mashups nested table end-user programming

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Improving Entity Linking in Chinese Domain by Sense Embedding Based on Graph Clustering

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Journal of Computer Science & Technology 2023年第1期38卷 196-210页

作者：张照博钟芷漫袁平鹏金海 National Engineering Research Center for Big Data Technology and System Huazhong University of Science and Technology Wuhan 430074China Service Computing Technology and System Laboratory Huazhong University of Science and Technology Wuhan 430074China Cluster and Grid Computing Laboratory Huazhong University of Science and TechnologyWuhan 430074China School of Computer Science and Technology Huazhong University of Science and TechnologyWuhan 430074China

Entity linking refers to linking a string in a text to corresponding entities in a knowledge base through candidate entity generation and candidate entity *** is of great significance to some NLP(natural language processing)tasks,such as question *** English entity linking,Chinese entity linking requires more consideration due to the lack of spacing and capitalization in text sequences and the ambiguity of characters and words,which is more evident in certain *** Chinese domains,such as industry,the generated candidate entities are usually composed of long strings and are heavily *** addition,the meanings of the words that make up industrial entities are sometimes *** semantic space is a subspace of the general word embedding space,and thus each entity word needs to get its exact ***,we propose two schemes to achieve better Chinese entity ***,we implement an ngram based candidate entity generation method to increase the recall rate and reduce the nesting ***,we enhance the corresponding candidate entity ranking mechanism by introducing sense *** the contradiction between the ambiguity of word vectors and the single sense of the industrial domain,we design a sense embedding model based on graph clustering,which adopts an unsupervised approach for word sense induction and learns sense representation in conjunction with *** test the embedding quality of our approach on classical datasets and demonstrate its disambiguation ability in general *** confirm that our method can better learn candidate entities’fundamental laws in the industrial domain and achieve better performance on entity linking through experiments.

关键词： natural language processing(NLP) domain entity linking computational linguistics word sense disambiguation knowledge graph

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Toward High-Performance Delta-Based Iterative Processing with a Group-Based Approach

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Journal of Computer Science & Technology 2022年第4期37卷 797-813页

作者： Hui Yu Xin-Yu Jiang Jin Zhao Hao Qi Yu Zhang Xiao-Fei Liao Hai-Kun Liu Fu-Bing Mao Hai Jin National Engineering Research Center for Big Data Technology and System Huazhong University of Science and TechnologyWuhan 430074China Service Computing Technology and System Laboratory Huazhong University of Science and TechnologyWuhan 430074China Cluster and Grid Computing Laboratory Huazhong University of Science and TechnologyWuhan 430074China School of Computer Science and Technology Huazhong University of Science and TechnologyWuhan 430074China

Many systems have been built to employ the delta-based iterative execution model to support iterative algorithms on distributed platforms by exploiting the sparse computational dependencies between data items of these iterative algorithms in a synchronous or asynchronous approach. However, for large-scale iterative algorithms, existing synchronous solutions suffer from slow convergence speed and load imbalance, because of the strict barrier between iterations;while existing asynchronous approaches induce excessive redundant communication and computation cost as a result of being barrier-free. In view of the performance trade-off between these two approaches, this paper designs an efficient execution manager, called Aiter-R, which can be integrated into existing delta-based iterative processing systems to efficiently support the execution of delta-based iterative algorithms, by using our proposed group-based iterative execution approach. It can efficiently and correctly explore the middle ground of the two extremes. A heuristic scheduling algorithm is further proposed to allow an iterative algorithm to adaptively choose its trade-off point so as to achieve the maximum efficiency. Experimental results show that Aiter-R strikes a good balance between the synchronous and asynchronous policies and outperforms state-of-the-art solutions. It reduces the execution time by up to 54.1% and 84.6% in comparison with existing asynchronous and the synchronous models, respectively.

关键词： iterative algorithm delta-based execution model efficiency

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RTGA: A Redundancy-free Accelerator for High-Performance Temporal Graph Neural Network Inference 24

RTGA: A Redundancy-free Accelerator for High-Performance Tem...

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61st ACM/IEEE Design Automation Conference, DAC 2024

作者： Yu, Hui Zhang, Yu Tan, Andong Lu, Chenze Zhao, Jin Liao, Xiaofei Jin, Hai Liu, Haikun National Engineering Research Center for Big Data Technology and System Service Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology China

ISBN: (纸本)9798400706011

Temporal Graph Neural Network (TGNN) has attracted much research attention because it can capture the dynamic nature of complex networks. However, existing solutions suffer from redundant computation overhead and excessive off-chip communications for TGNN inference because they often rely on redundant graph sampling and repeatedly fetching the features and vertex memory. This paper proposes a redundancy-free accelerator, RTGA, for high-performance TGNN inference. Specifically, RTGA proposes a redundancy-aware execution approach with temporal tree into a novel accelerator design to effectively eliminate unnecessary data processing for fewer redundant computations and off-chip communications and also designs a temporal-aware data caching method to improve data locality for TGNN. We have implemented and evaluated RTGA on a Xilinx Alveo U280 FPGA card. Compared with cutting-edge software solutions (i.e., TGN and TGL) and hardware solutions (i.e., BlockGNN and FlowGNN), RTGA improves the performance of TGNN inference by an average of 473.2x, 87.4x, 8.2x, and 6.9x and saves energy by 542.8x, 102.2x, 9.4x, and 8.3x, respectively. © 2024 Copyright is held by the owner/author(s). Publication rights licensed to ACM.

关键词： Spatio-temporal data

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