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作者： Park, Yunseo Lee, Chang-Ho Cressler, John D. Laskar, Joy IEEE Georgia Electronic Design Center Georgia Institute of Technology Atlanta GA 30332-0250 United States Georgia Tech. Research Faculty Georgia Tech. Georgia Tech. Department of Electrical and Computer Engineering Department of Electronic Design and Applications Technical Interest Group Georgia's Electronic Design Center Packaging Research Center Georgia Institute of Technology

The design of ultra-wideband (UWB) low-noise amplifiers (LNAs) require additional circuit design principles, which differ from those used in conventional LNAs. The design of a low-dc-power-consumption SiGe HBT LNA covering the 2-10-GHz range is demonstrated for UWB applications. Important design factors that must be carefully considered for UWB applications are analyzed, which include power dissipation, operating bandwidth, noise figure, group delay variation, and linearity. The dominant factor for low group delay variation in UWB LNAs is identified through the theoretical analysis. The linearity behavior over the wide bandwidth is analyzed and explained using the Volterra series. Second-harmonic cancellation is determined to be the dominant degradation factor for linearity. The implemented SiGe LNA achieves a gain of 13 dB, a minimum noise figure of 3.3 dB, and an input third-order intercept point of -7.5 dBm between 2-10 GHz while consuming a dc power of only 9.6 mW. This SiGe UWB LNA exhibits less than 22 ps of uniform group delay variation over the entire band. © 2006 IEEE.

关键词： Amplifiers (electronic)

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A new structure for capacitor-mismatch-insentive multiply-by-two amplification

A new structure for capacitor-mismatch-insentive multiply-by...

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ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems

作者： Zare-Hoseini, Hashem Shoaei, Omid Kale, Izzet Applied DSP and VLSI Research Group Department of Electronic Systems University of Westminster London Applied DSP and VLSI Research Centre Eastern Mediterranean University KKTC Mersin 10 Gazimagusa IC Design Laboratory Electrical and Computer Engineering Department University of Tehran Tehran Iran

ISBN: (纸本)0780393902

A new approach to achieve a switched-capacitor multiply-by-two gain-stage with reduced sensitivity to capacitors' mismatches is presented in this paper. It is based on sampling fully differential input signals onto both plates of the input capacitors rather than sampling onto one plate of the capacitors with the other tied to a reference. It uses one operational amplifier (op-amp) in two phases to produce the gain of two (×2). Comparing to the conventional multiply-bytwo gain-stage, the mismatches between the capacitors has a much smaller influence on the accuracy of the gain of two (×2). Analytical and circuit-level analysis of the architecture and the conventional structure are presented using a generic 0.35μm CMOS technology. © 2006 IEEE.

关键词： Capacitors

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Energy drivers for materials research and development

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Energy Materials: Materials Science and engineering for Energy Systems 2006年第1期1卷 1-6页

作者： Hald, John Viswanathan, Vis Abe, Fujio Manufacturing Engineering and Management Technical University of Denmark Denmark Materials Application EPRI Palo AltoCA United States Heat Resistant Design Group Steel Research Centre National Institute for Materials Science 1-2-1 Sengen Tsukuba Japan

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Efficient Modeling of Package Power Delivery Networks with Fringing Fields and Gap Coupling in Mixed Signal Systems

Efficient Modeling of Package Power Delivery Networks with F...

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IEEE Topical Meeting on Electrical Performance of Electronic Packaging (EPEPS)

作者： Krishna Bharath Ege Engin Madhavan Swaminathan Kazuhide Uriu Toru Yamada Packaging Research Centre School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA USA EMC Design Group System Engineering Center Matsushita Elecrric Indusrrial Company Limited Japan

Full-wave EM simulations are computationally expensive given the complexity of packaging structures in modern mixed signal systems. Fast methods such as the transmission matrix method are inaccurate as they do not model discontinuities such as metal edges and gaps. In this paper, simple models for the edge effect and gap coupling are developed for the finite difference frequency domain method. Results are presented comparing the accuracy of the proposed method with full-wave simulations and measurements

关键词： Power system modeling Electronics packaging Finite difference methods Frequency domain analysis Circuit simulation Equivalent circuits Microstrip design engineering Coupling circuits Radio frequency

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On the reliability issues of RF CMOS devices

On the reliability issues of RF CMOS devices

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ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology

作者： Wong, Hei Fu, Yue Liou, J.J. Yue, Yun Iwai, Hiroshi Dept. of Electronic Engineering City University of Hong Kong Tat Chee Avenue Kowloon Hong Kong Frontier Collaborative Research Center Tokyo Institute of Technology Nagatsuta Yokohama 226-8502 Japan Department of Electrical and Computer Engineering University of Central Florida Orlando FL 32816 United States RF/MS Design Group Conexant Systems Palm Bay FL 32905 United States

ISBN: (纸本)1424401615

Although multi-finger MOS structures have demonstrated very attractive behaviors for high-frequency analog circuit applications, the shared drain and source regions for adjacent gate fingers have led to current crowding and results in the finger number-dependent current-voltage characteristics. In addition, the high current density spots near the drain region would deteriorate the MOS reliability in several aspects. Present results suggest that the common drain regions should be wider and more heavily doped in order to alleviate these effects. © 2006 IEEE.

关键词： CMOS integrated circuits

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Failure analysis system for submicron semiconductor devices

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Hitachi Review 2006年第2期55卷 68-72页

作者： Fukui, Munetoshi Mitsui, Yasuhiro Nara, Yasuhiko Yano, Fumiko Furukawa, Takashi Application Technology Department Advanced Equipment and Systems Sales Division Hitachi High-Technologies Corporation Advanced Microscope Systems Design Department Nanotechnology Products Business Group Hitachi High-Technologies Corporation Failure Analysis Technology Group Process and Device Analysis Engineering Development Department Renesas Technology Corp. Advanced Technology Research Department Central Research Laboratory

Failure analysis of semiconductor device is becoming increasingly difficult as VLSI technology evolves toward smaller features and semiconductor device structures become more complex. Especially considering that the defective area obtained through diagnosis pin-pointing faulty sites is not the same size as the area subjected to physical analysis, and this disparity becomes more pronounced as feature sizes shrink. This prompted us to develop an extremely fine scaled SEM mechanical probing system permitting identification of minute fault sites. The development involved a number of related projects including investigation of a precision probe and stage mechanism that can deal with submicron semiconductor devices, a six-probe mechanism for expanded capabilities of performing inverter measurements and precision single transistor measurements, a probe and sample exchange mechanism that works while under vacuum to achieve high throughput, and a robust CAD navigation system. The system is now ready and available for practical application to 65-nm feature devices, and can be readily adapted to at least the next couple of generation nodes.

关键词： Failure analysis

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Stopband prediction with dispersion diagram for electromagnetic bandgap structures in printed circuit boards

Stopband prediction with dispersion diagram for electromagne...

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IEEE International Symposium on Electromagnetic Compatibility (EMC)

作者： Y. Toyota A.E. Engin Tae Hong Kim M. Swaminathan K. Uriu Department of Communication Network Engineering Okayama University Okayama Japan Packaging Research Center School of Electrical and Computer Engineering Georgia Institute of Technology USA Packaging Research Center School of Electrical and Computer Engineering Georgia Institute of Technology USA EMC Design Group System Engineering Center Matsushita Elecrric Indusrrial Company Limited Japan

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Taming the Complexity of STE-based design Verification Using Program Slicing

Taming the Complexity of STE-based Design Verification Using...

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IEEE International High-Level design Validation and Test Workshop

作者： Vivekananda M. Vedula Flemming L. Andersen Jacob A. Abraham Design and Technology Solutions Intel Corporation TX USA Corporate Technology Group Intel Corporation Hillsboro OR USA Computer Engineering Research Center University of Texas Austin Austin TX USA

This paper presents the development of a hierarchical methodology for speeding-up a symbolic trajectory evaluation (STE) based verification flow, using "program slicing" techniques. An overview of the proposed methodology is described, along with the details of a prototype tool that has been developed to automate the approach. The tool, called FACTOR, has been successfully applied to reduce the size of the RTL implementation of a floating-point unit in an Intelreg Pentiumreg 4 processor model needed for formally verifying an embedded module. The existing proof specification for the module was validated using Forte, Intel's STE tool, on both the original and the reduced model. A comparison of the results demonstrates the effectiveness of the methodology, and its immense potential to scale up the verification flow to larger design sizes

关键词： Boolean functions Circuit simulation Data structures Hardware design languages Space exploration System testing Conferences Jacobian matrices Prototypes Product development

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Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals

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IEEE Circuits and Systems Magazine 2006年第1期6卷 8-26页

作者： Baschirotto, A. Castello, Rinaldo Campi, Fabio Cesura, Giovanni Toma, Mario Guerrieri, Roberte Lodi, Andrea Lavagno, Luciano Malcovati, Piero Department of Electronics University of Pavia Italy STMicroelectronics Italy Advanced Research Center on Electronic Systems University of Bologna Italy Department of Electronics Politecnico di Torino Italy Department of Electrical Engineering University of Pavia Italy Department of Central Research and Development ST Microelectronics Italy Bologna Italy Department of Electronics University of Pavia Italy Italy Solid State Circuit Society IEEE Italy IEEE Italy Semiconductor Laboratory Max Planck Institute of Terrestrial and Extrater- Restrial Physics Munich Germany New IP and Design Support of the Computer and Peripheral Group of ST-Microelectronics University of Bologna Italy Politecnico di Torino Italy Cadence Berkeley Laboratories United States STMicroelectronics Italy Bologna Italy Department of Electrical Engineering University of Pavia Italy CR and D ST-Microelectronics Agrate Brianza Italy

Multimedia applications are driving wireless network operators to add high-speed data services such as Edge (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF freguency, signal bandwidth, modulation scheme, etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above-mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different reguirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or to reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design reguirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-interoperability. This paper presents analog and digital base-band circuits that are able to support GSM (with Edge), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the reguired QoS (Quality of Service) level. © 2006 IEEE.

关键词： computer terminals

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A new structure for capacitor-mismatch-insensitive multiply-by-two amplification

A new structure for capacitor-mismatch-insensitive multiply-...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： H. Zare-Hoseini O. Shoaei I. Kale Applied DSP and VLSI Research Group Department of Electronic Systems University of Westminster London UK IC Design Laboratory Electrical and Computer Engineering Department University of Tehran Tehran Iran KKTC Eastern Mediterranean University Gazi Magusa Mersin Turkey

A new approach to achieve a switched-capacitor multiply-by-two gain-stage with reduced sensitivity to capacitors' mismatches is presented in this paper. It is based on sampling fully differential input signals onto both plates of the input capacitors rather than sampling onto one plate of the capacitors with the other tied to a reference. It uses one operational amplifier (op-amp) in two phases to produce the gain of two (times2). Comparing to the conventional multiply-by-two gain-stage, the mismatches between the capacitors has a much smaller influence on the accuracy of the gain of two (times2). Analytical and circuit-level analysis of the architecture and the conventional structure are presented using a generic 0.35mum CMOS technology

关键词： Capacitors Operational amplifiers Sampling methods Digital signal processing Very large scale integration Feedback Circuit analysis Energy consumption Transfer functions Voltage

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