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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： H. Hartje I. Neumann D. Stoffel W. Kunz Fault Tolerant Computing Group University of Potsdam Potsdam Germany Electronic Design Automation Group University of Frankfurt Germany Electronic Design Automation Group University of Frankfurt Frankfurt Germany

ISBN: (纸本)0780366859

We present new concepts to integrate logic synthesis and physical design. Our methodology uses general Boolean transformations as known from technology-independent synthesis, and a recursive bi-partitioning placement algorithm. In each partitioning step, the precision of the layout data increases. This allows effective guidance of the logic synthesis operations for cycle time optimization. An additional advantage of our approach is that no complicated layout corrections are needed when the netlist is changed.

关键词： Timing Circuit synthesis Wire design optimization Integrated circuit interconnections Logic circuits Logic design Delay estimation fault tolerance Partitioning algorithms

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Cell replication and redundancy elimination during placement for cycle time optimization 99

Cell replication and redundancy elimination during placement...

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IEEE International Conference on Computer-Aided design

作者： I. Neumann D. Stoffel H. Hartje W. Kunz Department of Computer Science Electronic Design Automation Group Johann Wolfgang Goethe-University of Frankfurt Frankfurt Germany Department of Computer Science Fault Tolerant Computing Group University of Potsdam Potsdam Germany

ISBN: (纸本)9780780358324

Presents a new timing-driven approach for cell replication tailored to the practical needs of standard cell layout design. Cell replication methods have been studied extensively in the context of generic partitioning problems. However, until now, it has remained unclear what practical benefit can be obtained from this concept in a realistic environment for timing-driven layout synthesis. Therefore, this paper presents a timing-driven cell replication procedure, demonstrates its incorporation into a standard cell placement and routing tool, and examines its benefit on the final circuit performance in comparison with conventional gate or transistor sizing techniques. Furthermore, we demonstrate that cell replication can deteriorate the stuck-at fault testability of circuits and show that stuck-at redundancy elimination must be integrated into the placement procedure. Experimental results demonstrate the usefulness of the proposed methodology and suggest that cell replication should be an integral part of the physical design flow complementing traditional gate sizing techniques.

关键词： Timing Circuit testing Circuit synthesis Redundancy Delay Computer science Logic testing Automatic test pattern generation Electronic design automation and methodology Circuit faults

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Distributed self-diagnosis of VLSI mesh array processors

Distributed self-diagnosis of VLSI mesh array processors

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VLSI Test Symposium

作者： M. Cutler S.Y.H. Su M. Wang Research Group on Design Automation and Fault-Tolerant Computing Department of Computer Science State University of New York Binghamton Binghamton NY USA

A distributed self-diagnosis algorithm for VLSI mesh arrays with small clusters of faults is presented. It allows only fault-free cells to make decisions and to propagate diagnosis results. Its time complexity is cons... 详细信息

关键词： Very large scale integration fault diagnosis Automatic testing Distributed computing Clustering algorithms Test pattern generators System testing design automation Computer science Signal processing

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fault isolation in grey systems

Fault isolation in grey systems

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IEEE International Test Conference

作者： S.Y.H. Su H. Ma Research Group on Design Automation and Fault-tolerant Computing Thomas J. Watson School of Engineering Applied Science and Technology State University of New York Binghamton Binghamton NY USA

The concepts of grey, white, and black systems are formally introduced and developed into logic testing area, i.e. the area of error detection and fault isolation, to find a direction to establish more efficient test schemes for testing digital systems at a reasonable cost. A probabilistic isolation strategy realized by a heuristic and decision-making algorithm is presented to isolate faults in grey systems efficiently in terms of computation space and time.< >

关键词： Circuit testing Digital systems System testing Circuit faults Logic testing Costs Integrated circuit testing Integrated circuit interconnections fault detection Decision making

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designs for diagnosability and reliability in VLSI systems

Designs for diagnosability and reliability in VLSI systems

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IEEE International Test Conference

作者： S.Y.H. Su H. Ma Department of Computer Science Research Group on Design Automation and Fault-tolerant Computing Thomas J. Watson School of Engineering Applied Science and Technology State University of New York Binghamton Binghamton NY USA Department of Electrical Engineering Research Group on Design Automation and Fault-tolerant Computing Thomas J. Watson School of Engineering Applied Science and Technology State University of New York Binghamton Binghamton NY USA

Novel concepts of designs for diagnosability and reliability are defined and developed. A diagnosable design of VLSI system is presented, in which fault isolation is realized by minimal additional hardware instead of traditional software diagnostic procedures such that the computation space and time for fault isolation are saved. The presented fault-tolerant design uses online fault detection and isolation techniques, yields higher reliability with minimized hardware overhead of no more than 125% as opposed to over 200% in classical redundancy fault-tolerant designs. Using this scheme, the ability to isolate intermittent faults is a significant improvement over existing fault isolation methods because faults could be isolated right after they are detected.< >

关键词： Very large scale integration Circuit faults fault detection Costs Hardware Automatic testing Digital systems fault tolerance Redundancy Electrical fault detection

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FUNCTIONAL TEST GENERATION OF DIGITAL LSI/VLSI SYSTEMS USING MACHINE SYMBOLIC EXECUTION TECHNIQUE.

FUNCTIONAL TEST GENERATION OF DIGITAL LSI/VLSI SYSTEMS USING...

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Proceedings - International Test Conference 1984, The Three Faces of Test: design, Characterization, Production.

作者： Lin, Tonysheng Su, Stephen State Univ of New York Research Group on Design Automation & Fault-Tolerant Computing State Univ of New York Research Group on Design Automation & Fault-Tolerant Computing Bingham

ISBN: (纸本)0818605480

This paper presents a new algorithm for functional test generation of digital LSI/VLSI systems. First, a register-transfer (RT)-level fault model is developed based on a well-defined register-transfer-language (RTL). The analysis and collapsing of faults in RT-level fault model were performed. Then, the RT-level symbolic execution technique is employed. The major problems encountered are defined, analyzed and solved. Finally, an explicit algorithmic test generation algorithm is developed. This practical algorithm applies software skills in hardware testing. It is easy to be automated and hence provides a promising solution for future testing problems of digital LSI/VLSI systems.

关键词： INTEGRATED CIRCUITS, VLSI

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Functional Testing Techniques for Digital LSI/VLSI Systems 84

Functional Testing Techniques for Digital LSI/VLSI Systems

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design automation Conference

作者： S.Y.H. Su Tonysheng Lin Research Group on Design Automation and Fault-Tolerant Computing Department of Computer Science Thomas J. Watson School of Engineering Applied Science and Technology State University of New York Binghamton NY

ISBN: (纸本)9780818605420

Functional testing is becomilng more important due to the increasing complexity in digital LSI/VLSI devices. Various functional testing approaches have been proposed to meet this urgent need in LSI/VLSI testing. This paper presents the basic ideas behind deterministic functional testing and concisely overviews eight major functional testing techniques. Comparisons among these techniques and suggestions for future development are made to meet the challenges in this fast growing testing field.

关键词： System testing Large scale integration Very large scale integration Circuit testing Logic testing Circuit faults Automatic testing Integrated circuit testing Performance evaluation design automation

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RELIABILITY MEASURE OF HARDWARE REDUNDANCY fault-tolerant DIGITAL-SYSTEMS WITH INTERMITTENT faultS

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IEEE TRANSACTIONS ON COMPUTERS 1981年第8期30卷 600-604页

作者： MALAIYA, YK SU, SYH Research Group on Design Automation and Fault-Tolerant Computing School of Advanced Technology State University of New York

While significant results are available which allow estimation of reliability measure for systems with permanent faults, no generally applicable results are available for intermittent (transient) faults. Methods are presented here which allow reliability evaluation for systems with both intermittent and permanent faults. Two reliability measures, instantaneous and durational reliabilities, are defined and methods to compute them are given. Computed results for the durational reliability for various redundancy schemes are compared.

关键词： fault-tolerant design Markov model fault-tolerant system hardware redundancy intermittent faults modeling of faults multiple faults permanent faults reconfiguration scheme reliability analysis reliability evaluation transient faults

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Detecting bridging and stuck-at faults at input and output pins of standard digital components 80

Detecting bridging and stuck-at faults at input and output p...

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17th Annual ACM IEEE design automation Conference, DAC 1980

作者： Karpovsky, Mark Su, Stephen Y.H. Research Group on Design Automation and Fault-tolerant Computing School of Advanced Technology State University of New York BinghamtonNY13901 United States

ISBN: (纸本)0897910206

Due to the advances in the integrated circuit technology, there is an increasing importance in testing bridging (short circuit) failures in digital networks. Unfortunately, very little work has been done in this area. This paper presents the schemes for the detection of feedback bridgings between the inputs and outputs through the observation of oscillation and asynchronous behavior of sequential networks created'by bridging faults. The lower and upper bounds on the number of tests for detecting all feedback bridging faults are given. Conditions for the undetectability of input bridgings are given and a method for testing input bridgings is presented. The results are generalized to detect bridging and stuck-at faults in the input and output lines of a multipleoutput network. Finally, the complete test sets are given for detecting input, output and feedback bridgings as well as stuck-at faults at the Input and output pins of the standard integrated circuit chips including shift registers, counters, decoders, multiplexers, adders/subtracters, multipliers, dividers and RAM. Future unsolved problems in this area are also given. © 1980 ACM.

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