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architecture recovery for product families

引用

5th International Workshop on Product Family Engineering, PFE 2003

作者： Pinzger, Martin Gall, Harald Girard, Jean-Francois Knode, Jens Riva, Claudio Pasman, Wim Broerse, Chris Wijnstra, Jan Gerben Distributed Systems Group Vienna University of Technology Vienna Austria Institute for Experimental Software Engineering Fraunhofer Kaiserslautern Germany Software Architecture Group Nokia Research Center Helsinki Finland Philips Medical Systems Eindhoven Netherlands Philips Research Laboratories Eindhoven Netherlands

ISBN: (纸本)3540219412

software product families are rarely created right away but they emerge when a domain becomes mature enough to sustain their long-term investments. The typical pattern is to start with a small set of products to quickly enter a new market. As soon as the business proves to be successful new investments are directed to consolidating the software assets. The various products are migrated towards a flexible platform where the assets are shared and new products can be derived from. In order to create and maintain the platform, the organization needs to carry out several activities such as recovering the architectures of single products and product families, designing the reference architecture, isolating the variable parts, and generalizing software components. In this paper, we introduce a product family construction process that exploits related systems and product families, and we describe methods and tools used. We also present an approach for classifying platforms according to platform coverage and variation and describe three techniques to handle variability across single products and whole product families. © Springer-Verlag Berlin Heidelberg 2004.

关键词： Product design

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Teletraffic generation of self-similar processes with arbitrary marginal distributions for simulation: Analysis of hurst parameters

Teletraffic generation of self-similar processes with arbitr...

引用

International Conference on Computational Science and its Applications, ICCSA 2004

作者： Jeong, Hae-Duck J. Lee, Jong-Suk R. Park, Hyoung-Woo Department of Computer Science and Software Engineering University of Canterbury Christchurch New Zealand Grid Technology Research Department Supercomputing Centre Korea Institute of Science and Technology Information Daejeon Korea Republic of

ISBN: (纸本)3540220577

Simulation studies of telecommunication networks require a mechanism to transform self-similar processes into processes with arbitrary marginal distributions. The problem of generating a self-similar process of a given marginal distribution and an autocorrelation structure is difficult and has not been fully solved. Our results presented in this paper provide clear experimental evidence that the long-range dependent (LRD) self-similarity of the input process is not preserved in the output process generated by the inverse cumulative distribution function (ICDF) transformation, if the output process has an infinite variance. On the basis of our results we formulate the following hypothesis: If the ICDF transformation is applied to LRD self-similar processes with normal marginal distributions, then it preserves H parameter of the input process if the output marginal distribution has a finite variance. © Springer-Verlag Berlin Heidelberg 2004.

关键词： Distribution functions

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Semantic caching services for data grids

引用

3rd International Conference on Grid and Cooperative Computing, GCC2004

作者： Wan, Hai Hao, Xiao-Wei Zhang, Tao Li, Lei Department of Computer Science and Technology SUN YAT-SEN University Guangzhou510275 China Software Research Institute of SUN YAT-SEN University Guangzhou510275 China

ISBN: (纸本)3540235647

Semantic caching services are very attractive for acting as core services to deliver and share data in Data Grids considering the large sizes of requested data, prolonged data transmission time, and low reliable network. This paper provides semantic caching services for Data Grids and presents the services’ formal definitions, modeling, query processing, optimization and coherency control scheme. Finally, the performance of the semantic caching services for Data Grids is examined through a simulation study. © Springer-Verlag Berlin Heidelberg 2004.

关键词： Artificial intelligence

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On efficient and effective association rule mining from xml data

引用

15th International Conference on Database and Expert Systems Applications, DEXA 2004

作者： Zhang, Ji Ling, Tok Wang Bruckner, Robert M. Tjoa, A. Min Liu, Han Department of Computer Science University of Toronto TorontoONM5S 3G4 Canada Department of Computer Science National University of Singapore 117543 Singapore Microsoft Research RedmondWA United States Institute of Software Technology Vienna University of Technology Vienna Austria

ISBN: (纸本)3540229361

In this paper, we propose a framework, called XAR-Miner, for mining ARs from XML documents efficiently and effectively. In XAR-Miner, raw XML data are first transformed to either an Indexed Content Tree (IX-tree) or Multirelational databases (Multi-DB), depending on the size of XML document and memory constraint of the system, for efficient data selection in the AR mining. Concepts that are relevant to the AR mining task are generalized to produce generalized meta-patterns. A suitable metric is devised for measuring the degree of concept generalization in order to prevent under-generalization or overgeneralization. Resultant generalized meta-patterns are used to generate large ARs that meet the support and confidence levels. An efficient AR mining algorithm is also presented based on candidate AR generation in the hierarchy of generalized meta-patterns. The experiments show that XAR-Miner is more efficient in performing a large number of AR mining tasks from XML documents than the state-of-the-art method of repetitively scanning through XML documents in order to perform each of the mining tasks. © Springer-Verlag Berlin Heidelberg 2004.

关键词： XML

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Parallel programmable finite field GF (2/sup m/) multipliers

Parallel programmable finite field GF (2/sup m/) multipliers

引用

IEEE computer Society Annual Symposium on VLSI

作者： N. Iliev J.E. Stine N. Jachimiec VLSI Computer Architecture Arithmetic and CAD Research Laboratory Department of Electrical and Computer Engineering Illinois Institute of Technology Chicago IL USA

Block (cyclic) channel coding standards for third generation cellular networks require the implementation of high-performance burst-error detection and correction algorithms. Galois field (GF) arithmetic is commonly used in this architecture for encoding and decoding error codes, however, many architectures still do not support dedicated functional units. This paper presents the design of a generic parallel finite-field GF (2/sup m/) multiplier targeted at DSP and embedded processors. As opposed to previous research, this design has the ability to utilize different primitive polynomials as an input, thereby, being able to be programmable. Moreover, a design is presented that is a combined binary and finite-field GF (2/sup m/) multiplier. Area, delay, and power dissipation results are presented from several ASIC libraries.

关键词： Galois fields Channel coding Land mobile radio cellular systems Arithmetic Decoding Digital signal processing Polynomials Delay Power dissipation Application specific integrated circuits

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Planar orthogonal drawing of complete binary trees inside rectilinear polygons

Planar orthogonal drawing of complete binary trees inside re...

引用

IEEE International Conference on Multi Topic

作者： A. Bagheri M. Razzazi Software Systems Research & Development Lab Department of Computer Engineering & IT Amirkabir University of Technology슠 Tehran Iran Software Systems Research & Development Lab Department of Computer Engineering & IT Institute for Studies in Theoretical Physics and Mathematics (I.P.M) Amirkabir University of Technology슠 Tehran Iran

In this paper we introduce a new algorithm for planar orthogonal drawing of complete binary trees on the surface of a given simple rectilinear polygon. Our algorithm aims to uniformly distribute the vertices of the given tree on the given surface and to reduce the total number of edge bends as much as possible. We also introduce a new linear time algorithm for bisecting simple (rectilinear) polygons, assuming the straight skeletons of the polygons are given. To our knowledge, this paper and the previous works of the authors are the first attempts for developing algorithms that draw trees on 2D surfaces which are bounded by simple (rectilinear) polygons.

关键词： Binary trees Tree graphs Skeleton Engineering drawings Application software Very large scale integration Graphical user interfaces research and development Optical computing Physics computing

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Performance of new broadcast forwarding criteria in MANET

引用

International Conference on Information Networking, ICOIN 2004

作者： Zhu, Lijuan Lee, Bu-Sung Seet, Boon-Chong Wong, Kai-Juan Liu, Genping Huang, Shell-Ying Lee, Keok-Kee Centre for Multimedia and Network Technology School of Computer Engineering Singapore Network Technology Research Centre Research TechnoPlaza Nanyang Technological University 4th Storey Nanyang Avenue 639798 Singapore Institute for Computing Systems Architecture Informatics University of Edinburgh JCMB Mayfield Road EdinburghEH9 3JZ United Kingdom

ISBN: (纸本)3540230343

In a mobile ad hoc network (MANET), packet broadcast is common and frequently used to disseminate information. Broadcast consume large amount of bandwidth resource, which is scarce in MANET environment. The problem is to find the ideal forward node set so as to minimize the bandwidth consumed, which is a NP-Complete problem. In this paper we will investigate three dominant node approximation algorithms: dominant pruning, total dominant pruning and partial dominant pruning algorithm. An extension to the original algorithms, modified termination criteria, is proposed. Simulation results show that the new termination criteria ensure the same coverage using a reduced number of forward nodes. © Springer-Verlag Berlin Heidelberg 2004.

关键词： Approximation algorithms

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A routing strategy for metropolis vehicular communications

引用

International Conference on Information Networking, ICOIN 2004

作者： Liu, Genping Lee, Bu-Sung Seet, Boon-Chong Foh, Chuan-Heng Wong, Kai-Juan Lee, Keok-Kee Centre for Multimedia and Network Technology School of Computer Engineering Singapore Network Technology Research Centre Research TechnoPlaza Nanyang Technological University 4th Storey Nanyang Avenue 639798 Singapore Institute for Computing Systems Architecture Informatics University of Edinburgh JCMB Mayfield Road EdinburghEH9 3JZ United Kingdom

ISBN: (纸本)3540230343

One of the major issues that affect the performance of mobile ad hoc networks (MANET) is routing. Recently, position-based routing for MANET is found to be a very promising routing strategy for inter-vehicular communication systems (IVCS). However, position-based routing for IVCS in a built-up city environment faces greater challenges because of potentially more uneven distribution of vehicular nodes, constrained mobility, and difficult signal reception due to radio obstacles such as high-rise buildings. This paper proposes a new position-based routing scheme called Anchor-based Street and Traffic Aware Routing (A-STAR), designed specifically for IVCS in a city environment. Unique to A-STAR is the usage of information on city bus routes to identify an anchor path with high connectivity for packet delivery. Along with a new recovery strategy for packets routed to a local maximum, the proposed protocol shows significant performance improvement in a comparative simulation study with other similar routing approaches. © Springer-Verlag Berlin Heidelberg 2004.

关键词： Stars

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CODACS prototype: CHIARA language and its compiler

CODACS prototype: CHIARA language and its compiler

引用

International Conference on Distributed Computing Systems Workshop

作者： L. Verdoscia M. Danelutto R. Esposito Institute for High Performance Computing and Networking National Research Council Napoli Italy Department of Computer Science University of Pisa Pisa Italy Research Centre On Software Technology University of Sannio Benevento Italy

We present CHIARA, the programming language used to program CODACS (a general purpose dataflow architecture exploiting FPGA technology), and describe the compiling strategies leading from CHIARA programs to the CODACS dataflow graphs. CHIARA is a functional programming language based on Backus'FP. We designed both the language and the compiling tools in such a way that CHIARA programs can be efficiently compiled and run onto the overall architecture and CODACS platform-processors being, for the latter, also the low-level (assembly) programming language. Some preliminary experimental results are discussed, demonstrating that the CHIARA approach to CODACS programming is feasible and promising.

关键词： Prototypes computer languages Field programmable gate arrays computer architecture Parallel processing Program processors High performance computing Functional programming Hardware Assembly

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X-masking during logic BIST and its impact on defect coverage

X-masking during logic BIST and its impact on defect coverag...

引用

IEEE International Test Conference

作者： Yuyi Tang H.-J. Wunderlich H. Vranken F. Hapke M. Wittke P. Engelke I. Polian B. Becker Institute of Computer Architecture and Computer Engineering University of Stuttgart Stuttgart Germany Philips Research Laboratories Eindhoven The Netherlands Philips Semiconductors GmbH Design Technology Center Hamburg Germany Institute for Computer Science Albert-Ludwigs-University Freiburg I. Br Germany

We present a technique for making a circuit ready for logic BIST by masking unknown values at its outputs. In order to keep the silicon area cost low, some known bits in output responses are also allowed to be masked. These bits are selected based on a stuck-at n-detection based metric, such that the impact of masking on the defect coverage is minimal. An analysis based on a probabilistic model for resistive short defects indicates that the coverage loss for unmodeled defects is negligible for relatively low values of n.

关键词： Built-in self-test Logic testing Circuit testing Logic circuits Circuit faults Automatic testing Silicon Costs Clocks XML

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