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Solving the problems of Routing Interconnects with a Resynthesis for Reconfigurable Systems on a Chip

Russian microelectronics 2018年第7期47卷 516-521页

作者： Gavrilov, S.V. Zheleznikov, D.A. Khvatov, V.M. Institute of Design Problems in Microelectronics Russian Academy of Sciences Moscow Russia National Research University MIET Moscow Russia

Abstract: The existing means of design automation are focused mainly on the technology of foreign manufacturers, which makes it necessary to adapt the existing methods and means for designing reconfigurable systems-on-a-chip and to develop domestic specialized CAD tools to solve urgent problems in this field. Methods are proposed for solving interconnection routing problems in conjunction with logical resynthesis, applied to the architecture of a reconfigurable system-on-a-chip based on the domestic field-programmable gate array (FPGA) of the Almaz-14 family. Developers from JSC "NIIME" and PJSC "Micron" laid broad configurational solutions, which do not have foreign analogues, into this crystal. A wide range of additional elements for the configuration, as well as the potentialities for the logical resynthesis of the FPGA Almaz-14 chip, have led to the need to develop new methods for routing interconnections that would allow us to take into account and use these architectural features. An efficient algorithm for the automatic routing of interconnections for a reconfigurable system on a chip based on FPGAs belonging to the Almaz-14 family based on algorithm A* is developed. This algorithm represents a modification of the classical algorithm searching for the shortest path on a graph, the Dijkstra algorithm, including a mixed switching graph model. To describe the variety of additional switching elements, a special generalized mathematical model, as well as a special interface in the command language Tcl are developed, the latter includes a list of elements for configuration, as well as their description and functional purpose. This work has increased the efficiency of computer-aided design using programmed mechanisms developed and implemented in the C programming language for the optimal use of the configuration and routing elements of FPGAs, as well as mechanisms for the complete and entire routing of interconnections. © 2018, Pleiades Publishing, Ltd.

关键词： Computer aided design

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Automatic FPGA Placement Configuration for Customer designs

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Russian microelectronics 2022年第7期51卷 579-584页

作者： Enns, V.I. Gavrilov, S.V. Chochaev, R. Zh. Research Institute of Molecular Electronics Moscow124460 Russia Institute for Design Problems in Microelectronics Russian Academy of Sciences Moscow124681 Russia

Abstract: Specialization of configurable heterogeneous ICs for specific customer proposals requires the flexibility of design and technological solutions. This, in turn, leads to the necessity of the automatic adjustment of CAD, including software placement tools, on the changes made. The development of efficient methods and tuning algorithms is impossible without relying on the appropriate mathematical apparatus. This study presents a set-theoretic mathematical model of a hierarchical project and formalizes a hierarchical approach to the netlist using the apparatus of set theory, mathematical logic, and graph theory. To ensure quick configuration of clustering and placement software tools, taking into account the changes made to the basic design, the correspondence between the elements of the basic FPGA design and user-designed circuits from the end user is formalized. The obtained results can serve as a base for the development of the efficient methods and algorithms for the automatic tuning of software clustering and placement tools. © 2022, Pleiades Publishing, Ltd.

关键词： Field programmable gate arrays (FPGA)

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Antenna Array Calibration Algorithm without Access to Channel Signals

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Radioelectronics and Communications Systems 2020年第1期63卷 1-14页

作者： Djigan, Victor I. Kurganov, Vladislav V. Institute for Design Problems in Microelectronics of Russian Academy of Sciences Moscow Russia National Research University of Electronic Technology Moscow Russia

This paper describes the algorithm of antenna array (AA) calibration, which estimates and compensates phase lags, caused by non-identical electrical characteristics of array channels. The algorithm does not require the access to the channel signals or the channels disabling. It uses only the array output power measurements under the specific channel phase perturbations. The algorithm accuracy equals the phase shifter quantization step, i.e. it is twice less than phase shifter accuracy itself and does not depend on the number of array channels. The algorithm accuracy is compared with two similar calibration algorithms, known from publications. The compared algorithms accuracy depends on the number of array channels and is much less than the proposed algorithm. Thus, the new algorithm can be widely used for the efficient AA calibration, signal source angular position estimation and tracking by a calibrated or a non-calibrated AA with any aperture shape: linear, flat or conformal, with an arbitrary distance between neighbor AA elements and with an arbitrary antenna selected as a reference one. © 2020, Allerton Press, Inc.

关键词： Phase shifters

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Pathfinder Algorithm Modification for FPGA Routing Stage

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Russian microelectronics 2022年第7期51卷 573-578页

作者： Zapletina, M.A. Gavrilov, S.V. Institute for Design Problems in Microelectronics of the Russian Academy of Sciences Moscow Russia National Research University of Electronic Technology Moscow Russia

Abstract: One of the main advantages of FPGA design flow is the high development speed;therefore, the importance of effective computer-aided design tools for modern microcircuits of these classes cannot be overestimated. Placement and routing are the most time-consuming stages of FPGA design flow. The quality of results of these stages is crucial to the final performance of custom digital circuits implemented on FPGA. The paper discusses an approach to accelerating the routing stage within the layout synthesis flow for FPGA by introducing a few algorithmic improvements to a routing procedure. The basic routing algorithm under study is a modified Pathfinder for a mixed routing resources graph. Pathfinder is a well-known negotiation-based routing algorithm that works on the principle of iteratively eliminating congestions of chip routing resources. The sets of test digital circuits ISCAS’85, ISCAS’89, LGSynth’89 and several custom industrial projects were used for computational experiments. The impact of the proposed algorithmic improvements was analyzed using four FPGA architectures. It has been established that due to the improvements of the algorithm proposed in the paper, the average reduction in routing time was from 1.3 to 2.6 times, depending on the FPGA architecture, with no significant negative effect on the timing characteristics of the designed circuits. © 2022, Pleiades Publishing, Ltd.

关键词： Field programmable gate arrays (FPGA)

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TCAD Modeling of Nanoscale FinFET Structures on Bulk Silicon, Taking into Account the Effects of Radiation

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Russian microelectronics 2022年第7期51卷 545-551页

作者： Petrosyants, K.O. Silkin, D.S. Popov, D.A. Li, Bo Zhang, Xu National Research University Higher School of Economics Moscow Russia Institute for Design Problems in Microelectronics Russian Academy of Sciences Moscow Russia Institute of Microelectronics Chinese Academy of Sciences Beijing China

Abstract: The transition from planar MOSFET structures to 3D FinFET structures provides resistance to various types of radiation. However, the characteristics of irradiated devices created at different manufacturers differ significantly, and it is rather difficult to explain the dependence of the radiation resistance of FinFE-T structures on variations in their physical and topological parameters and electrical modes. We develop a radiation version of the TCAD model of a FinFET MOSFET on bulk silicon. Additional semiempirical radiation dependences specific for FinFET structures for the effective mobility of charge carriers and the concentration of traps in the volumes of SiO2 and HfO2 oxides and at the oxide–silicon interfaces are introduced in the basic model of a nanometer MOSFET. The model is implemented in the Sentaurus Synopsys TCAD environment. The model is validated on a test set of FinFET structures with a channel length of 60 to 7 nm without irradiation and in the range of gamma irradiation doses up to 1 Mrad. A comparison of the static current-voltage characteristics obtained by simulation with the experimental results showed an error not exceeding 15%. © 2022, Pleiades Publishing, Ltd.

关键词： Ionizing radiation

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Simulating the Self-Heating Effect for MOSFETs with Various Configurations of Buried Oxide

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Russian microelectronics 2019年第7期48卷 467-469页

作者： Petrosyants, K.O. Popov, D.A. National Research University Higher School of Economics Moscow Russia Institute for Design Problems in Microelectronics Russian Academy of Sciences Moscow Russia

Abstract: SOI MOSFETs have the worst properties of heat removal from an active region, which negatively affects the reliability and efficiency of integrated circuits. Using TCAD modeling, we investigate the self-heating effect in the following structures of deeply submicron MOSFETs with different configurations of buried oxide: traditional bulk MOSFET, SOI structure, SELBOX structure, partial SOI structure, thin-BOX SOI structure, UTBB SOI structure, and quasi-SOI structure. It is shown that, for a number of new designs, the maximum temperature in the MOSFET structure is significantly reduced as compared to max of the standard SOI MOSFET structure;it approaches the values typical of standard MOSFETs on bulk silicon. © 2019, Pleiades Publishing, Ltd.

关键词： Silicon on insulator technology

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Adaptive Arrays for GNSS Receivers 3

Adaptive Arrays for GNSS Receivers

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3rd IEEE International Conference on problems of Informatics, Electronics and Radio Engineering, PIERE 2024

作者： Djigan, Victor I. National Research Center 'Kurchatov Institute' Department of Design Problems in Microelectronics Moscow Russia

ISBN: (纸本)9798331516321

An adaptive antenna array of the land-based equipment of the Global Navigation Satellite System has to be able to accept the signals from a several satellites and to suppress a several interfering signals simultaneously. The side lobe canceller is one of the widely used adaptive arrays to do this job. Unfortunately, this array does not ensure any specified value of its radiation pattern towards any direction except the directions towards the interfering signal sources. As a result, this array does not ensure the same conditions for the reception of the signals from all visible satellites. The problem solution, which is proposed in this paper, is to use the linearly constrained array instead of the side lobe canceller. A single constraint in a form of a fixed radiation pattern value towards the normal to the array aperture (zenith direction) allows to produce a beam which is always steered towards this direction in spite of the radiation pattern changing caused by the interfering signals cancellation. This ensures a stable reception of the signals at least from the satellites whose angular locations are within the array beam. The performance of a circular linearly constrained array and a circular side lobe canceller of the nine omnidirectional antennas is compared by means of simulation. A better performance of the circular linearly constrained array comparing to the circular linearly constrained array is demonstrated. This is ensured by a wider beam with a bigger gain of the linearly constrained array. This beam allows to receive the signals from a larger number of visible satellites. These results suggest a preferable usage of the linearly constrained arrays against the side lobe cancellers in the receivers of the Global Navigation Satellite System. © 2024 IEEE.

关键词： Omnidirectional antennas

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Features of TCAD and SPICE Simulation of a Charged Particle Impact into a 6T SRAM Cell Manufactured Using the CMOS 28-nm Technology Node

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Russian microelectronics 2024年第7期53卷 737-743页

作者： Petrosyants, K.O. Silkin, D.S. Popov, D.A. Ismail-Zade, M.R. Kharitonov, I.A. Pereverzev, L.E. Morozov, A.A. Turgenev, P.V. National Research University Higher School of Economics Moscow Russia Institute for Design Problems in Microelectronics Russian Academy of Sciences Moscow Russia ООО AlphaCHIP Moscow Russia

Abstract—: With a decrease in the size of transistors, the conditions arise when the impact of one particle affects several transistors in the composition of a memory cell. Therefore, during simulation it is not sufficient to take into account one transistor directly hit by a particle. In this study, a full-size 3D model of two n-channel transistors that are part of a 6T memory cell in which the charged particle enters is considered. A particle impact simulation procedure is proposed that makes it possible to calculate the current pulse after the impact in a TCAD simulator and the response of memory cell circuit to an impact in a SPICE simulator using SPICE models. This procedure allows combining the advantages of the TCAD and SPICE calculations and achieve consistency between accuracy and the speed of simulation. The issues of determining the parameters of the TCAD model of a particle impact, the occurrence of a current pulse after a particle impact near a transistor in the on state, and the influence of the current of this transistor on the operation of a memory cell are considered. A technique of specifying the complex distribution profiles of charge carriers induced by particle impact in a TCAD simulator is proposed. Several cases of particle impact with different linear energy transfer (LET) values are simulated and an example of determining the critical LET value for a 6T SRAM cell with a design code of 28 nm is shown. The tailored parameters of the physical structure of the transistor make it possible to simulate the characteristics of transistors manufactured using the 28-nm CMOS technology node. © Pleiades Publishing, Ltd. 2024.

关键词： CMOS integrated circuits

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FPGA Routing Architecture Estimation Models and Methods

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Russian microelectronics 2021年第7期50卷 509-515页

作者： Chochaev, R. Zh. Zheleznikov, D.A. Ivanova, G.A. Gavrilov, S.V. Enns, V.I. Institute for Design Problems in Microelectronics Russian Academy of Sciences Moscow124681 Russia National Research University of Electronic Technology Moscow124498 Russia Molecular Electronics Research Institute Moscow124460 Russia

Abstract: The problem of analyzing and evaluating the structure of FPGA routing resources at the early stages of the design flow is of a great interest for researchers. Until now, an approach, consisting of running the full design flow (logic synthesis, placement, routing) on a set of test circuits with a subsequent estimation of various parameters for each FPGA architecture being analyzed, had been dominant. Despite the high accuracy, this approach has a long runtime and requires lots of computing resources, as well as CAD tuned to the analyzed FPGA architecture. Modern FPGA contains more than a million logical gates, therefore, the application of such an approach is inefficient. Today, more attention is paid to the development of various models, which allows the evaluation of the structure of the routing resources at early stages without using the benchmark circuits. In this work, an overview of the existing models and methods for analyzing the structure of FPGA routing resources is presented. A comparison of the methods and models is performed, the estimation of their efficiency and possibility of application for designing domestic FPGA is made. It is found that the most optimal approach for analyzing arbitrary structures of the routing resources FPGA is the development and application of mixed methods. This will allow to obtain accurate models as well as to significantly reduce the development and market entry time. © 2021, Pleiades Publishing, Ltd.

关键词： Field programmable gate arrays (FPGA)

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Evaluation of the Effect of FinFET Structure Parameters on Electrical Characteristics Using TCAD Modeling Tools

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Russian microelectronics 2022年第8期51卷 644-648页

作者： Petrosyants, K.O. Silkin, D.S. Popov, D.A. National Research University Higher School of Economics Moscow101000 Russia Institute for Design Problems in Microelectronics Russian Academy of Sciences Moscow124681 Russia

Abstract: Using TCAD modeling, the effect of changing the FinFET structure parameters, such as gate stack layer sizes, fin shape, or doping levels, on the electrical characteristics of the device is studied. © 20... 详细信息

关键词： FinFET

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