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检索条件"机构=Research Institute of Design Problems in Microelectronics"

共 86 条记录，以下是41-50 订阅

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Simple Algorithm of Antenna Array Calibration

Simple Algorithm of Antenna Array Calibration

引用

Siberian Conference on Control and Communications (SIBCON)

作者： Vladislav Kurganov Victor Djigan Institute of Microdevices and Control Systems National Research University of Electronic Technology (MIET) Moscow Russia Institute for Design Problems in Microelectronics of RAS Moscow Russia

ISBN: (纸本)9781728185040;9781728185057

This paper presents a simple algorithm for the calibration of antenna arrays. It belongs to the phase-less algorithms family, because it does not require the expensive phase measurement equipment. The estimation and compensation of the complex-valued gains of the array channels, caused by non-identical characteristics of these channels, is the aim of a calibration task. For the estimation, the considered calibration algorithm uses only three measurements of the array output power under 0°, 90° and 270° phase shifter states in each channel. The algorithm explanation and the main steps of the algorithm development, based on the geometrical representation of the antenna array signals, are presented. The algorithm efficiency is proved via simulation.

关键词： Phased arrays Phase measurement Power measurement Phase shifters Channel estimation Estimation Calibration

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Electro-thermal modeling of trench-isolated SiGe HBTs using TCAD

Electro-thermal modeling of trench-isolated SiGe HBTs using ...

引用

IEEE Symposium on Semiconductor Thermal Measurement and Management (SEMI-THERM)

作者： K. O. Petrosyants R. A. Torgovnikov National Research University Higher School of Economics Moscow Institute of Electronics and Mathematics Moscow Russia Russian Academy of Sciences Institute for Design Problems in Microelectronics

ISBN: (纸本)9781479985968

The modern SiGe HBT structure with shallow and deep trench isolation (STI and DTI) is analyzed from electrothermal standpoint using TCAD system. The electrical parameters β, f T , f max , maximal temperature T max , and thermal resistance R TH are under consideration. TCAD simulation confirms the fact that the presence of STI and DTI in SiGe HBT structures gains the self-heating effect in comparison with traditional Si BJT structures, where DTI is not used. It is shown that for high power regimes (I C = 0.5-3 mA; V CE = 4-5 V) the set of electrical parameters β, f T , f max significantly degrade, temperature T max can reach the critical values about 500 K, and the thermal resistance RTH increases thrice in HBT structure with STI and DTI. These results agree with published experimental data.

关键词： Silicon germanium Heterojunction bipolar transistors Diffusion tensor imaging Silicon Temperature distribution Heating Thermal resistance

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Antenna Arrays Calibration Using Recursive Least Squares Adaptive Filtering Algorithms Based on Inverse QR Decomposition

Antenna Arrays Calibration Using Recursive Least Squares Ada...

引用

East-West design & Test Symposium (EWDTS)

作者： Victor Djigan Vladislav Kurganov Department of Integrated Circuits Design Methodology Institute for Design Problems in Microelectronics of RAS Moscow Russia Institute of Microdevices and Control Systems National Research University of Electronic Technology Moscow Russia

ISBN: (数字)9781728198996

ISBN: (纸本)9781728199009

This paper considers the antenna arrays calibration by the using of the Recursive Least Squares (RLS) adaptive filtering algorithms. An algorithm, based on the inverse QR decomposition, has been selected among the diversity of the RLS algorithms. This is caused by its stable operation. Because the algorithm contains the computationally heavy square root operations, a square root free version of the algorithm is also presented. Both versions of the QR RLS algorithms are mathematically identical to each other if they operate in float point arithmetic. The proposed calibration can be used in the antenna arrays with digital beamforming, because the algorithms usage requires the access to the array channel signals. The calibration requires a known training signal, which can be easily provided not only in a laboratory environment, but also in a field operation, if an array is used as a directional antenna of the digital communication system equipment. In the second case, the calibration can be also conducted even in the presence of the interference signal sources. Simulation validates the proposed calibration algorithm, using linear antenna arrays with 4, 8 and 16 antennas with a half wavelength distance between the neighbor antennas. In this simulation, the array channel noise has been varied in 0 ... 30 dB range of the Signal-to-Noise Ratio. Two interference sources with the -30 dB Signal-to-Interference Ratio each have been simulated. These sources were located symmetrically relatively the required main lobe direction of the array radiation pattern. A training signal has been simulated as a random one with no specific autocorrelation properties. The signal has been modulated by the Phase Shift Keying (PSK) and the Quadrature Amplitude Modulation.

关键词： Calibration Interference Filtering algorithms Signal processing algorithms Matrix decomposition Correlation Array signal processing

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Clustered voltage scaling design technique for low-power hashing unit

Clustered voltage scaling design technique for low-power has...

引用

East-West design & Test Symposium (EWDTS)

作者： Andrey Korshunov Pavel Volobuev Alexander Stempkovsky Sergey V. Gavrilov Daria Ryzhova National Research University of Electronic Technology Moscow Russia Institute for Design Problems in Microelectronics of Russian Academy of Sciences (IPPM RAS) Moscow Russia

This work is focused on a technique providing the integration of the method of clustered voltage scaling (CVS) in the digital design flow. The efficiency of this technique in the case of a hashing unit IP-block is considered. In order to reduce the power consumption special hash algorithms (NH, PH) in combination with the CVS approach were proposed. For the implementation of the CVS technique a number of standard cells have been developed: level shifters and flip-flops with level conversion. The simulation results have showed that developed hashing unit with the CVS technique allows - decreasing power consumption on average by 12% with area penalty about 3% and without timing degradation.

关键词： Delays Wireless sensor networks Power demand Standards Flip-flops Logic gates

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Differential clock cross-point correction method for pipeline ADCs

Differential clock cross-point correction method for pipelin...

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East-West design & Test Symposium (EWDTS)

作者： Arsen Hekimyan Sergey Gavrilov Davit Trdatyan Arman Trdatyan National Research University of Electronic Technology Moscow Russia Problems in Microelectronics (IPPM RAS) Research Institute for Design Moscow Russia Synopsys Armenia CJSC Yerevan Armenia

ISBN: (纸本)9781509006946

Differential clock cross point correction method is presented in this paper. The proposed method provides differential clock with minimum crossing error over PVT, which is needed to improve noise immunity of Pipeline ADC. As Pipeline ADC work with differential clock, so crossing error of differential clock could decrease noise immunity. Cross point correction method also helps to avoid setup/hold violations in some systems. Proposed architecture can be used in different architecture of Pipeline ADCs, in the special input/output circuits of several standards such as Universal Serial Bus (USB) Peripheral Component Interconnect (PCI) and Double Data Rate (DDR).

关键词： Clocks Detectors Pipelines Error correction microelectronics Universal Serial Bus Low-pass filters

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design of CMOS amplifiers with extended temperature range

Design of CMOS amplifiers with extended temperature range

引用

IEEE NW Russia Young researchers in Electrical and Electronic Engineering Conference (EIConRusNW)

作者： A. Solovev E. Balaka V. Ruhlov Yu. Adamov National Research University of Electronic Technology-MIET Moscow Russian Federation Institute for Design Problems in Microelectronics of Russian Academy of Sciences Moscow Russian Federation

design of CMOS amplifiers with extended temperature range is considered. Comparison of the proposed solutions has been conducted. Stabilization is achieved by the use of feedback.

ISBN: (纸本)9781509048663

design of CMOS amplifiers with extended temperature range is considered. Comparison of the proposed solutions has been conducted. Stabilization is achieved by the use of feedback.

关键词： MOSFET Temperature distribution Low-pass filters Differential amplifiers Logic gates

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Methods of logical synthesis for library elements and blocks with regular layout structure

Methods of logical synthesis for library elements and blocks...

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IEEE International Conference on Electronics and Nanotechnology (ELNANO)

作者： Sergey Gavrilov Galina Ivanova Pavel Volobuev Aram Manukyan The Institute for Design Problems in Microelectronics Russian Academy of Science Moscow Zelenograd Russia National Research University of Electronic Technology (MIET) Moscow Zelenograd Russia

The paper is devoted to research and development of custom IP-blocks design methods in the form of standard elements with regular layout structure in the layers of polysilicon and diffusion. For today the leading developers of microelectronic devices continue to work out the key modules of microelectronic systems, such as core microprocessors, microcontrollers completely custom-made in a mode in which the final composition of library elements is not known beforehand, and the design is extremely low at the transistor level. However, automation of logic and layout synthesis process for a completely custom design is difficult due to significant increase in the complexity of the problem with increasing integration of microelectronic systems and decreasing the size of the standard elements to 22nm and below. The authors proposed FinFET layout design formation methods for layout synthesis of elements with a regular layout structure in layers of polysilicon and diffusion.

关键词： Layout Logic gates FinFETs Standards Integrated circuit modeling Libraries

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SPICE Modeling of Small-Size Bulk, SOI and SOS MOSFETs at Deep-Cryogenic Temperatures

SPICE Modeling of Small-Size Bulk, SOI and SOS MOSFETs at De...

引用

International Workshop on Thermal Investigation of ICs and Systems (THERMINIC)

作者： Mamed R. Ismail-zade Konstantin O. Petrosyants Lev M. Sambursky Xu Zhang Bo Li Jiajun Luo Zhengsheng Han National Research University Higher School of Economics (Moscow Institute of Electronics and Mathematics) Moscow Russia Institute for Design Problems in Microelectronics of Russian Academy of Sciences Moscow Russia Institute of Microelectronics of Chinese Academy of Sciences Beijing China

A set of modified compact SPICE models of various flavours of MOSFETs (fabricated by bulk, SOI and SOS technologies) is presented for circuit simulation in the deep-cryogenic temperature range down to 4 K, which is important for space applications and development of scalable quantum computers. All models are constructed using the approach combining macromodeling based on the standard models available in the library of SPICE models and introducing smooth analytical functions continuous with temperature for the model parameters. A unified automated procedure for model parameter extraction is presented for all the models, providing an acceptable accuracy of accounting for electrical and temperature effects for practical applications in the temperature range from room temperature to 4 K.

关键词： Semiconductor device modeling Temperature distribution Analytical models MOSFET Computational modeling Cryogenics SPICE

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Real-time Object Detection with FPGA Using CenterNet

Real-time Object Detection with FPGA Using CenterNet

引用

IEEE NW Russia Young researchers in Electrical and Electronic Engineering Conference (EIConRusNW)

作者： Roman A. Solovyev Dmitry V. Telpukhov Irina I. Romanova Alexander G. Kustov Ilya A. Mkrtchan Institute for Design Problems in Microelectronics of Russian Academy of Sciences (IPPM RAS) Moscow Russia School of Economics National Research University Higher Moscow Russia

ISBN: (数字)9781665404761

ISBN: (纸本)9781665446426

the paper proposes methodology for transferring architecture of modern neural network CenterNet to FPGA. CenterNet is a OneStage object detector that is used to detect and locate objects in images. Although this neural network has simple decoder, it shows good performance in terms of accuracy. Very high operation speed of the neural network hardware is achieved due to the choice of suitable encoder and efficient hardware implementation of both the decoder and the last layer with object filtering, and also transition to fixed-point arithmetic. At this, quality of the obtained predictions remains high.

关键词： Neural network hardware Object detection Logic gates Real-time systems Hardware Decoding Field programmable gate arrays

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Application of exhaustive search, branch and bound, parallel computing and Monte-Carlo methods for the synthesis of quasi-optimal network-on-chip topologies

Application of exhaustive search, branch and bound, parallel...

引用

East-West design & Test Symposium (EWDTS)

作者： Aleksandr Romanov Irina Romanova Alexander Ivannikov National Research University Higher School of Economics Moscow Russian Federation The Institute for Design Problems in Microelectronics of Russian Academy of Sciences Moscow Russian Federation

On the basis of an integrated network-on-chip (NoC) topologies optimality criterion, as well as applying the adjacency matrix to describe NoC topologies, exhaustive search method and its modification by using branch and bound and Monte-Carlo methods are extended to the synthesis of NoC quasi-optimal topologies. designed ScaNoC suboptimal topology synthesis algorithm is implemented on a high-level programming language which makes it possible to generate quasi-optimal topological solutions in accordance with the requirements to reduce hardware costs and the average distance between nodes. Proposed quasioptimal topologies synthesis algorithm improvement by using the method of parallel computing allows speeding up the process of synthesis to 2 117 times and getting topologies with the number of nodes up to 18.

关键词： Topology Network topology Symmetric matrices Algorithm design and analysis Parallel processing Search methods Program processors

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