Hardware-software subsystem designed for MOSFETs characteristic measurement and SPICE model parameter extraction taking into account radiation effects is presented. Parts of the system are described. The macromodel ap...
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Hardware-software subsystem designed for MOSFETs characteristic measurement and SPICE model parameter extraction taking into account radiation effects is *** of the system are *** macromodel approach is used to accoun...
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Hardware-software subsystem designed for MOSFETs characteristic measurement and SPICE model parameter extraction taking into account radiation effects is *** of the system are *** macromodel approach is used to account for radiation effects in MOSFET *** of the account for radiation effects in MOSFETs within the measurement and model parameter extraction procedures are *** of the subsystem is illustrated on the example of radiation hardened 0.25 μm SOI MOSFET test structures.
Automated electro-thermal analysis is realized in the last version of Mentor Graphics PCB design System. The special software tool AETA is developed and integrated into the Expedition Enterprise PCB design System to a...
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ISBN:
(纸本)9781479920976
Automated electro-thermal analysis is realized in the last version of Mentor Graphics PCB design System. The special software tool AETA is developed and integrated into the Expedition Enterprise PCB design System to automate the process of power-temperature traffic between electrical and thermal simulators. Furthermore AETA provides the graphical user interface and the possibility to use the different versions of Mentor Graphics software.
A comparison of delay time (td) for n- and p-MOSFETs switches with silicon on sapphire (SOS), silicon on insulator (SOI) and bulk silicon structures is presented. Two step TCAD-SPICE simulation procedure was used to d...
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A comparison of delay time (td) for n- and p-MOSFETs switches with silicon on sapphire (SOS), silicon on insulator (SOI) and bulk silicon structures is presented. Two step TCAD-SPICE simulation procedure was used to d...
详细信息
A comparison of delay time (td) for n- and p-MOSFETs switches with silicon on sapphire (SOS), silicon on insulator (SOI) and bulk silicon structures is presented. Two step TCAD-SPICE simulation procedure was used to define td for the set of 3.0...0.25 um MOSFETs fabricated by the three mentioned technologies. It was shown that 0.5 um Peregrine UTSi SOS n- and p-MOSFET provided the td reduction of 220-240% in comparison with bulk silicon and 20-25% with SOI.
Negative bias temperature instability (NBTI) has become a primary mechanism that degrades performance of integrated circuits. It is well known that NBTI impacts pMOS transistors during circuit operation, and the degra...
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Negative bias temperature instability (NBTI) has become a primary mechanism that degrades performance of integrated circuits. It is well known that NBTI impacts pMOS transistors during circuit operation, and the degradation occurs when pMOS transistor is in a conducting state. So, accurate NBTI degradation analysis requires analysis of logic states. Degradation of specific pMOS transistor depends on part of lifetime, in which this transistor is under stress, in other words, on stress probability. In this paper, we propose the correct algorithm of calculating stress probability for every pMOS transistor of complex CMOS gate. Comparing to simple "naive" approach, our algorithm takes into account two additional factors: correlations between signals at gate inputs, and VDD-potential coming through "bottom" of pMOS transistor. Numerical experiments show the importance of accounting for both these factors.
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