In the paper, the authors describe the improved operational amplifier architecture (op-amp). Complementary FETs with the p-n-junction control were used in the design of this op-amp, depletion-mode complementary MOS ca...
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ISBN:
(纸本)9781665464819
In the paper, the authors describe the improved operational amplifier architecture (op-amp). Complementary FETs with the p-n-junction control were used in the design of this op-amp, depletion-mode complementary MOS can also be used. The character of the suggested op-amp is to create conditions that contribute to obtaining low systematical constituent offset voltage (V off ), which significantly depends on the change in the drain-gate specifications of transistors when the static voltages on their drains change. It should be noted that the high symmetric of the static regimen of the input transistors and output transistors of the folded-cascode of the suggested op-amp is supplied to reduce this constituent V off in the considered op-amp circuit. Computer modelling of the op-amp carried out in the LTSpice was fulfilled in the large range of temperatures (from -197°C to 27°C). The suggested circuit design minimizes the systematical constituent V off (below 30 µV) and increases the open-loop gain of op-amp to 60 dB. The JFET op-amp circuitry suggested in the paper is advised to analog-to-digital and analog interfaces, incl. those operating at exposure to radiation and low temperatures.
This paper summarizes the cinematic demixing (CDX) track of the Sound Demixing Challenge 2023 (SDX’23). We provide a comprehensive summary of the challenge setup, detailing the structure of the competition and the da...
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The research of the orbit of the point zero, fixed points, Julia and Fatou sets for the iterated complex-valued exponential is carried by means of computer experiment. The object of study is three one-parameter famili...
The research of the orbit of the point zero, fixed points, Julia and Fatou sets for the iterated complex-valued exponential is carried by means of computer experiment. The object of study is three one-parameter families based on exp (iz): f : z → (1 + μ) exp (iz), g : z → (1 + μ|z − z*|) exp (iz), h : z → (1 + μ (z − z*)) exp (iz). Here. For the first family 17- and 2-periodic regimes are detected when passing near the bifurcation value μ ≈ 2.475i, while the multiplicator equals 1. The second family shows a more interesting behavior: (i) three-valley structure of isolines of the convergence rate near fixpoint z* at μ = 0 + 1 + i; (ii) saddle-node transition when the parameter moves along a straight line Reμ = 0, leading to the appearance of a second fixpoint and loss of stability by the old fixpoint at Imμ = 2.1682; (iii) the nontrivial nature of the orbits of points in the vicinity of the new fixpoint and the presence of false fixpoints in the portrait of the Julia set; (iv) second phase transition leading to a radical change in the form of the Julia and Fatou sets at μ 2.5i. The dynamics of the third family during movement at Reμ = 0 is similar to the first case, but 17th and 2nd periodic modes are replaced by 39th and 3rd modes. Transitions 17 → 2 and 39 → 3 seem to be rapid and discreet while their geometric interpretation matches the ratios 17=1+2*8, 39=13*3. At μ = |z*|−1 for the h- family Julia set fills the entire complex plane.
New second order high-pass filter of the Sallen-Key family circuit is considered, where there is unrelated tune of generic parameters by a digitally controlled resistor - the pole frequency, Q-factor pole and the scal...
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ISBN:
(数字)9781665498043
ISBN:
(纸本)9781665498050
New second order high-pass filter of the Sallen-Key family circuit is considered, where there is unrelated tune of generic parameters by a digitally controlled resistor - the pole frequency, Q-factor pole and the scale transfer coefficient. The basic mathematical expressions of transfer function for proposed high-pass filter are obtained. A comparison of the parameters of the known and new schemes is given. A Sallen-Key high-pass filter circuit based on a high-frequency emitter follower has been developed. The results of high-pass filter modeling in the Micro-Cap 12 environment using the OP37 operational amplifier and an ideal buffer amplifier are presented. Computer simulation has shown that the pole frequency is adjusted by resistor R5. Adjusting the pole attenuation is possible by changing the resistor R3, while the pole attenuation frequency unchanged, an increase in R3 leads to an increase of the pole attenuation.
New circuit techniques for increasing the performance of OAmps on Split-Length transistors in the input stage (IS) are considered. A promising architecture of high-speed micropower OAmps, which allows increasing SR by...
New circuit techniques for increasing the performance of OAmps on Split-Length transistors in the input stage (IS) are considered. A promising architecture of high-speed micropower OAmps, which allows increasing SR by 1-2 orders of the magnitude, is proposed in the article. The computer simulation results of the input stages throughput characteristics and study of the OAmp Slew Rate in Cadence OrCAD 16.6 environment on low-temperature models of AGAMC_2.1 transistors (JSC "Integral", Minsk) are presented, which confirm a significant increase in Slew Rate without increasing power consumption in static mode. The developed architecture of the high-speed OAmp is also promising for implementation on wide-gap semiconductors (GaAs, GaN, SiC, Si technologies) and for designing high-speed ADC drivers operating in harsh operating conditions (exposure to penetrating radiation and low temperatures).
The technique of circuit noise reduction of charge-sensitive amplifiers containing bipolar and junction field-effect transistors is considered. The initial and improved circuit of the integrated charge-sensitive ampli...
The technique of circuit noise reduction of charge-sensitive amplifiers containing bipolar and junction field-effect transistors is considered. The initial and improved circuit of the integrated charge-sensitive amplifiers using the above mentioned technique, the results of the step-by-step noise reduction when changing the sizes and operating modes of transistors, and improvement of the bias circuits are presented.
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