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Transparent random access memory testing for pattern sensitive faults

JOURNAL OF ELECTRONIC testing-THEORY AND APPLICATIONS 1996年第3期9卷 251-266页

作者： Karpovsky, MG Yarmolik, VN Research Laboratory of Design and Testing of Computer Hardware Department of Electrical Computer and Systems Engineering Boston University Boston USA

This paper presents a new methodology for RAM testing based on the PS(n, k) fault model (the k out of n pattern sensitive fault model). According to this model the contents of any memory cell which belongs to an n-bit memory block, or the ability to change the contents, is influenced by the contents of any k-1 cells from this block. The proposed methodology is a transparent BIST technique, which can be efficiently combined with on-line error detection. This approach preserves the initial contents of the memory after the rest and provides for a high fault coverage for traditional fault and error models, as well as for pattern sensitive faults. This paper includes the investigation of testing approaches based on transparent pseudoexhaustive testing and its approximations by deterministic and pseudorandom circular tests. The proposed methodology can be used for periodic and manufacturing testing and require lower hardware and time overheads than the standard approaches.

关键词： random access memory memory testing exhaustive memory testing transparent memory testing built-in self-test pseudo-exhaustive memory testing pattern sensitive faults signature analysis

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MLFuse: Multi-Scenario Feature Joint Learning for Multi-Modality Image Fusion

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IEEE Transactions on Multimedia 2025年

作者： Lei, Jia Li, Jiawei Liu, Jinyuan Wang, Bin Zhou, Shihua Zhang, Qiang Wei, Xiaopeng Kasabov, Nikola K. Dalian University Key Laboratory of Advanced Design and Intelligent Computing Ministry of Education School of Software Engineering Dalian116622 China University of Science and Technology Beijing School of Computer and Communication Engineering Beijing100083 China Dalian University of Technology School of Mechanical Engineering Dalian116024 China Dalian University of Technology School of Computer Science and Technology Dalian116024 China Auckland University of Technology Knowledge Engineering and Discovery Research Institute Auckland1010 New Zealand Ulster University Intelligent Systems Research Center LondonderryBT52 1SA United Kingdom

Multi-modality image fusion (MMIF) entails synthesizing images with detailed textures and prominent objects. Existing methods tend to use general feature extraction to handle different fusion tasks. However, these methods have difficulty breaking fusion barriers across various modalities owing to the lack of targeted learning routes. In this work, we propose a multi-scenario feature joint learning architecture, MLFuse, that employs the commonalities of multi-modality images to deconstruct the fusion progress. Specifically, we construct a cross-modal knowledge reinforcing network that adopts a multipath calibration strategy to promote information communication between different images. In addition, two professional networks are developed to maintain the salient and textural information of fusion results. The spatial-spectral domain optimizing network can learn the vital relationship of the source image context with the help of spatial attention and spectral attention. The edge-guided learning network utilizes the convolution operations of various receptive fields to capture image texture information. The desired fusion results are obtained by aggregating the outputs from the three networks. Extensive experiments demonstrate the superiority of MLFuse for infrared-visible image fusion and medical image fusion. The excellent results of downstream tasks (i.e., object detection and semantic segmentation) further verify the high-quality fusion performance of our method. The code is publicly available at https://***/jialei-sc/MLFuse. © 1999-2012 IEEE.

关键词： Semantic Segmentation

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Multidimensional fourier transforms by systolic architectures

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Journal of VLSI Signal Processing 1992年第4期4卷 343-354页

作者： Roziner, T.D. Karpovsky, M.G. Research Laboratory for Design and Testing of Computers and Communication Systems Department of Computer and Systems Engineering Boston University Boston 02215 Massachusetts 44 Cummington Street United States

In this paper, time-efficient systolic and semi-systolic architectures for the implementation of multidimensional DFTs are proposed that allow modularity and easy expansibility while keeping throughput independent of the dimension of the DFT. We shall call an array semi-systolic if the input data is to be preloaded into every cell of the array or if the output data can be calculated not only in the boundary cells of the array. DFT algorithms are represented by FORTRAN-like code, in order to explicitly display the suggested rotational transformations in the index space. After the transformation, multidimensional DFT algorithm can be mapped onto a systolic structure. The area-time² complexity of the proposed design is within log k factor of the lower bound for a k-point DFT (AT²=Ω(k² log²k)), i.e. equals 0(k² log³k)=0(N^{2 M} log³N) for k=N^{2 M} point DFT;A is the area complexity and T is the system throughput. © 1992 Kluwer Academic Publishers.

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Built-in self-diagnostic by space-time compression of test responses

Built-in self-diagnostic by space-time compression of test r...

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1992 IEEE VLSI Test Symposium, VLSI 1992

作者： Karpovsky, M.G. Chaudhry, S.M. Research Laboratory of Design and Testing of Computer Hardware Department of Electrical Computer and Systems Engineering Boston University BostonMA02215 United States

ISBN: (纸本)0780306236

Presents two different methodologies for built-in self-diagnostic of boards and systems by space-time compression of test responses. The first method, soft decision, uses nonbinary multiple error-correcting codes to obtain space-time signatures. These obtained signatures and the corresponding precomputed references are compared and magnitudes of distortions in signatures are analyzed to identify faulty components. The second method, hard decision, makes use of the information indicating whether the corresponding signatures are distorted or not. Both approaches show considerable savings in hardware overheads when compared with a straightforward approach where a separate signature is required for every component. A transition from the soft to hard decision approach results in an increase in the number of signatures required for diagnostic but at the same time it results in a decrease in the complexity of a fault locating algorithm. Results pertaining to VLSI implementations are presented where the hardware overhead is estimated in terms of two-input equivalent gates. © 1992 IEEE.

关键词： Data compression

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Access and resources reservation in 4G-VANETs for multimedia applications 13

Access and resources reservation in 4G-VANETs for multimedia...

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13th International Conference on Ad-hoc Networks and Wireless, ADHOC-NOW 2014 accompanied by 2nd International Workshop on Emerging Technologies for Smart Devices, ETSD 2014, 2nd International Workshop on Marine Sensors and systems, MARSS 2014, Multimedia Wireless ad hoc Networks, MWaoN 2014, Security in Ad Hoc Networks, SecAN 2014, 2nd Smart Sensor Protocols and Algorithms, SSPA 2014 and 8th International Workshop on Wireless Sensor, Actuator and Robot Networks, WiSARN 2014

作者： Garai, Mouna Mahjoub, Mariem Rekhis, Slim Boudriga, Noureddine Bettaz, Mohamed Communication Networks and Security Research Laboratory University of Carthage Tunis Tunisia Methods of Systems Design Laboratory National School of Computer Science Algiers Algeria

ISBN: (纸本)9783662463376

The development of Vehicular Ad-hoc Networks (VANET) has witnessed the release of various multimedia services and made it important to develop architectures and routing protocols capable of (a) handling the multimedia QoSs requirements and the real-time services’ constraints;(b) maximizing the network coverage;and (c) managing resources on the Road Side Units (RSUs), in order to guarantee the continuous delivery of real-time services. In this work, we provide a novel 4G-based VANET heterogeneous architecture, which integrates IEEE 802.11p and 3GPP LTE access networks, to provide access to multimedia services. A tree-based network access scheme is developed, providing a rapid connection and handover to highly mobility vehicles, and allowing to maximize at a large extent the network coverage beyond the area uncovered by RSUs (in the form of LTE eNodeBs). Techniques for the proactive resources provision on the RSUs, and the management of QoS-aware vertical and horizontal handovers, are developed. © Springer-Verlag Berlin Heidelberg 2015.

关键词： Vehicular ad hoc networks

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Board-level diagnosis by signature analysis

Board-level diagnosis by signature analysis

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IEEE International Test Conference

作者： M.G. Karpovsky P. Nagvajara Research Laboratory for Design and Testing of Computer and Communication Systems Computer and Communication Systems Computer and Communication Systems Department of Electrical Computer and System Engineering Boston University Boston MA USA

Board-level diagnostic techniques by signature analysis based on single-error-correcting Hamming codes over GF(2/sup M/) (where M is the number of outputs per chip) are presented. Two techniques are considered: the space-time compressor technique for the case when responses from N chips on the board are wired to the compressor; and the time compressor technique for the case when test responses from each chip are transferred to the compressor via system bus. Assuming a single-faulty-chip model, a faulty chip on the board under test is located by an analysis of the relationship between the distortions in the obtained signatures. Both techniques for board-level diagnosis require less hardware than the straightforward diagnostic techniques using a built-in signature analyzer for every chip or selective testing of each chip via the system bus, hence offering an efficient approach for a design of a built-in-self-test board for for manufacturing testing.< >

关键词： System testing System buses Hardware Built-in self-test Automatic testing Pattern analysis Fault diagnosis Laboratories design engineering systems engineering and theory

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Efficient test generation for built-in self-test boundary-scan template

Efficient test generation for built-in self-test boundary-sc...

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1991 IEEE VLSI Test Symposium: Chip-to-System Test Concerns for the 90''s, VTEST 1991

作者： Nagvajara, P. Karpovsky, M.G. Levitin, L.B. Dept. of Electr. and Comput. Eng. Drexel Univ. PhiladelphiaPA United States Research Laboratory for Design and Testing of Computer and Communication Systems Department of Electrical Computer and System Engineering Boston University United States

An analysis and design of a pseudorandom pattern generator, (PRPG), based on a linear recurrence, for built-in self-test (BIST) boundary scan design is presented. The authors present for the case when r≥s, a design of an s-stage PRPG capable of producing 2s-1 distinct r-bit patterns within 2s-1 clock pulses independent of the hardware realization of the PRPG. For the case when rr distinct r-bit patterns and the expected number T(N) of distinct patterns given a number N of clock pulses were presented. The proposed theoretical average N(T) was shown to be close to the experimental average values Nex(T). Hence, the value N(T) or T(N) can be used as a benchmark for evaluating the efficiency of a BIST boundary scan test generation. © 1991 IEEE.

关键词： Built-in self test

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Multidimensional Fourier transforms by systolic architectures

Multidimensional Fourier transforms by systolic architecture...

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International Conference on Databases, Parallel Architectures and Their Applications

作者： T.D. Roziner Research Laboratory for Design and Testing of Computer and Communication Systems College of Engineering Boston University Boston MA USA

A method of formal transformation of a multidimensional DFT (discrete Fourier transform) algorithm to a form suitable for implementation with a systolic macropipeline is discussed. The suggested transformation of the original form of the DFT algorithm consists of one or several rotationlike transforms applied to the index set. The resulting 'completely systolized' form of the algorithm makes it possible to implement the N/sup M/-point (m-dimensional) DFT with a macropipeline containing M or (M-1) cascaded systolic/semisystolic arrays. Each array is an M-dimensional hypercube of the processing elements (PEs) of the multiply-add type; the internal structure of PEs in different arrays is slightly different. For given values of N and M, several design options exist, with hardware complexity of about the same value. The proposed systolic architecture makes it possible to obtain the throughput of N (one set of spectrum values every N array clocks) for any number of dimensions M.< >

关键词： Multidimensional systems Fourier transforms Discrete Fourier transforms Throughput Very large scale integration Systolic arrays design for testability Circuits computer architecture Laboratories

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Detection and location of given sets of errors by nonbinary linear codes 1st

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1st French-Israeli Workshop on Algebraic Coding, 1993

作者： Karpovsky, Mark G. Chaudhry, Saeed M. Levitin, Lev B. Moraga, Claudio Research Laboratory of Design and Testing of Computer Hardware Department of Electrical Computer and Systems Engineering Boston University BostonMA02215 United States Department of Computer Science University of Dortmund Dortmund 504600 Germany

ISBN: (纸本)9783540578437

The problem of constructing codes capable of detection and location of a given set of errors is considered. Lower and upper bounds on a number of redundant symbols for an arbitrary set of errors are derived. These codes can be used for error detection and identification of faulty processing elements in multiprocessor systems. To this end, new classes of codes for several types of error sets such as stars, trees and FFTs meshes are presented. The concepts of strong and weak diagnostics (SD and WD, respectively) are introduced and discussed. © 1994, Springer Verlag. All rights reserved.

关键词： Location

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A generalized file replication scheme with diffusion-based storage load balancing function in unstructured P2P file-sharing networks

A generalized file replication scheme with diffusion-based s...

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2nd International Conference on Intelligent Networking and Collaborative systems, INCOS 2010

作者： Takaoka, Masanori Uchida, Masato Oie, Yuji NCOS Laboratory NEC Communication Systems Kanagawa Japan Graduate School of Computer Science and System Engineering Kyushu Institute of Technology Fukuoka Japan Network Design Research Center Kyushu Institute of Technology Tokyo Japan

ISBN: (纸本)9780769542782

In this paper, we provide a generalized file replication scheme with a storage load balancing function in unstructured P2P file-sharing networks. The generalized file replication scheme is expressed as a weighted mixture of the concepts introduced in existing schemes. A mathematical analysis shows that the system behavior realized by the generalized file replication scheme can be described by a thermal diffusion equation composed of heat, reaction and diffusion terms, the weights of which are controlled by a parameter of the mixing rate. Here, the heat term represents a function to enhance file search performance by making replicas on specific peers. The reaction term represents a function to avoid concentrations of storage loads on specific peers. The diffusion term represents a function to uniform the storage loads among peers. The simulation results show that the generalized file replication scheme enables us to control the trade-off between search and storage load balancing performances extensively and intuitively by controlling the parameter of the mixing rate. In addition, the simulation results show that the generalized file replication scheme can adapt to dynamic P2P file-sharing environments. © 2010 IEEE.

关键词： Economic and social effects

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