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International Symposium on Fault-Tolerant Computing (FTCS)

作者： M.G. Karpovsky S.M. Chaudhry L.B. Levitin Research Laboratory of Design and Testing of Computer Hardware Department of Electrical Computer and Systems Engineering Boston University Boston MA USA

A framework, based on nonbinary multiple error correcting codes, for built-in self-diagnostics is presented. Novel space-time compressors are proposed for test response compression and fault diagnosis. Fault-detecting and locating capabilities for space-time compressors are analyzed in the case when nonbinary Reed-Solomon codes are used. Fault-masking and diagnosis probabilities for the chip-independent error model are estimated. For this error-model, the fault-masking probabilities are analyzed using the weight distributions of Reed-Solomon codes.< >

关键词： Circuit faults Compressors Fault diagnosis Automatic testing System testing Built-in self-test Electrical fault detection Fault detection Error correction codes Laboratories

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Identification of faulty processing elements by space-time compression of test responses

Identification of faulty processing elements by space-time c...

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IEEE International Test Conference

作者： M.G. Karpovsky L.B. Levitin F.S. Vainstein Research Laboratory of Design and Testing of Computer Hardware Department of Electrical Computer and Systems Engineering Boston University Boston MA USA

A novel approach to the identification of a faulty processing element, based on an analysis of the compressed response of the system, is proposed. The test response is compressed first in space and then in time, and a faulty processing element is identified by a hard-decision decoding of the corresponding space-time signature. The overhead analysis and the solution for the hardware minimization problem are presented for several important classes of systems. The proposed method results in considerable hardware savings.< >

关键词： Fault diagnosis System testing Hardware design engineering Decoding Laboratories systems engineering and theory Educational institutions Vectors System buses

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Built-in self-diagnostic by space-time compression of test responses

Built-in self-diagnostic by space-time compression of test r...

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VLSI Test Symposium

作者： M.G. Karpovsky S.M. Chaudhry Research Laboratory of Design and Testing of Computer Hardware Department of Electrical Computer and Systems Engineering Boston University Boston MA USA

Presents two different methodologies for built-in self-diagnostic of boards and systems by space-time compression of test responses. The first method, soft decision, uses nonbinary multiple error-correcting codes to obtain space-time signatures. These obtained signatures and the corresponding precomputed references are compared and magnitudes of distortions in signatures are analyzed to identify faulty components. The second method, hard decision, makes use of the information indicating whether the corresponding signatures are distorted or not. Both approaches show considerable savings in hardware overheads when compared with a straightforward approach where a separate signature is required for every component. A transition from the soft to hard decision approach results in an increase in the number of signatures required for diagnostic but at the same time it results in a decrease in the complexity of a fault locating algorithm. Results pertaining to VLSI implementations are presented where the hardware overhead is estimated in terms of two-input equivalent gates.< >

关键词： Automatic testing Fault diagnosis System testing Hardware Error correction codes Built-in self-test Information analysis Laboratories design engineering systems engineering and theory

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Efficient test generation for built-in self-test boundary-scan template

Efficient test generation for built-in self-test boundary-sc...

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VLSI Test Symposium

作者： P. Nagvajara M.G. Karpovsky L.B. Levitin Department of Electrical and Computer Engineering Drexel University Philadelphia PA USA Research Laboratory for Design and Testing of Computer and Communication Systems Department of Electrical Computer and System Engineering Boston University Boston MA USA

An analysis and design of a pseudorandom pattern generator, (PRPG), based on a linear recurrence, for built-in self-test (BIST) boundary scan design is presented. The authors present for the case when r>or=s, a design of an s-stage PRPG capable of producing 2/sup s/-1 distinct r-bit patterns within 2/sup s/-1 clock pulses independent of the hardware realization of the PRPG. For the case when r >

关键词： Automatic testing Built-in self-test Circuit testing Clocks Test pattern generators Pulse generation Pattern analysis Laboratories System testing design engineering

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Advanced Layout design For Deep-submicron Cmos Output Buffer With Higher Driving Capability And Better Esd Reliability

Advanced Layout Design For Deep-submicron Cmos Output Buffer...

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International Symposium on VLSI Technology, systems and Applications

作者： Ming-Dlou Ker Chung-Yu Wu Tung-Yang Chen VLSI Design Department Computer & Communication Research Laboratories (CCL Industrial Technology and Research Institute Hsinchu Taiwan Integrated Circuits & Systems Laboratory Institute of Electronics National Chiao Tung University Hsinchu Taiwan

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CMOS on-chip ESD protection design with substrate-triggering technique

CMOS on-chip ESD protection design with substrate-triggering...

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IEEE International Conference on Electronics, Circuits and systems (ICECS)

作者： Ming-Dou Ker Tung-Yang Chen Chung-Yu Wu VLSI Design Division Computer & Communication Research Laboratories (CCL) Industrial Technology and Research Institute Hsinchu Taiwan Integrated Circuits and Systems Laboratory Institute of Electronics National Chiao Tung University Hsinchu Taiwan

To increase the ESD robustness and to reduce the trigger voltage of the ESD protection devices, a substrate-triggering technique is proposed to effectively enhance the ESD-protection efficiency of CMOS on-chip ESD protection circuits in submicron CMOS technologies. With suitable substrate bias, the ESD protection devices can sustain much higher ESD-stress voltage within small layout area. Two practical design examples of the input ESD protection circuit and the VDD-to-VSS ESD clamp circuit are designed by using the substrate-triggering technique to verify the ESD protection efficiency.

关键词： Electrostatic discharge Protection CMOS technology Voltage Robustness Clamps Integrated circuit modeling Pins Stress Variable structure systems

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ESD protection for deep-submicron CMOS technology using gate-couple CMOS-trigger lateral SCR structure

ESD protection for deep-submicron CMOS technology using gate...

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International Electron Devices Meeting (IEDM)

作者： Ming-Dou Ker Hun-Hsien Chang Chung-Yu Wu VLSI Design Department Computer & Communication Research Laboratories (CCL) Industrial Technology and Research Institute Hsinchu Taiwan Integrated Circuits and Systems Laboratory Institute of Electronics National Chiao Tung University Hsinchu Taiwan

ISBN: (纸本)0780327004

A novel ESD protection circuit, which first combines the advantages of complementary low-voltage-trigger SCR devices and the gate-couple technique, is proposed to more effectively protect the thinner gate oxide of deep submicron CMOS ICs without adding an extra ESD-implant mask. Experimental results have verified its excellent ESD-protection capability.

关键词： CMOS technology Electrostatic discharge Protection Thyristors Breakdown voltage Circuits MOS devices Stress CMOS process Robustness

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Whole-chip ESD protection scheme for CMOS mixed-mode IC's in deep-submicron CMOS technology

Whole-chip ESD protection scheme for CMOS mixed-mode IC's in...

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Custom Integrated Circuits Conference (CICC)

作者： Ming-Dou Ker Chung-Yu Wu Hun-Hsien Chang Tain-Shun Wu VLSI Design Department Computer & Communication Research Laboratories (CCL) Industrial Technology and Research Institute Hsinchu Taiwan Integrated Circuits & Systems Laboratory Institute of Electronics National Chiao Tung University Hsinchu Taiwan

ISBN: (纸本)0780336690

A whole-chip ESD protection scheme with the ESD-connection diodes and a substrate-triggering field-oxide device (STFOD) are proposed to protect mixed-mode CMOS IC's against ESD damage. The STFOD is triggered on by the substrate-triggering technique to make an area-efficient VDD-to-VSS ESD clamp circuit. The ESD-connection diodes provide the current discharging paths among the multiple separated power lines to avoid the ESD damage located at the digital-analog interface. This whole-chip ESD protection scheme has been practically verified in an L-bits DAC chip in a 0.6-/spl mu/m CMOS process with a pin-to-pin ESD robustness of above 4 KV.

关键词： CMOS technology Electrostatic discharge Protection CMOS integrated circuits Voltage Variable structure systems Diodes Pins Clamps Stress

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Multiscale Bilateral Attention Fusion Network for Pansharpening

IEEE Transactions on Artificial Intelligence

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IEEE Transactions on Artificial Intelligence 2024年第11期5卷 5828-5843页

作者： Guo, Zhongyuan Li, Jiawei Lei, Jia Liu, Jinyuan Zhou, Shihua Wang, Bin Kasabov, Nikola K. Dalian University Key Laboratory of Advanced Design and Intelligent Computing Ministry of Education School of Software Engineering Dalian116622 China University of the Science and Technology Beijing School of Computer and Communication Engineering Beijing100083 China Dalian University of Technology School of Mechanical Engineering Dalian116024 China Auckland University of Technology Knowledge Engineering and Discovery Research Institute Auckland1061 New Zealand University of Ulster Intelligent Systems Research Center LondonderryBT48 7JL United Kingdom Bulgarian Academy of Sciences IICT Sofia1000 Bulgaria

High-resolution multispectral (HRMS) images combine spatial and spectral information originating from panchromatic (PAN) and reduced-resolution multispectral (LRMS) images. Pansharpening performs well and is widely used to obtain HRMS images. However, most pansharpening approaches determine the ratio of PAN and LRMS images through direct interpolation, which may introduce artifacts and distort the color of the fused results. To address this issue, an unsupervised progressive pansharpening framework, MSBANet, is proposed, which adopts a multistage fusion strategy. Each stage contains an attention interactive extraction module (AIEM) and a multiscale bilateral fusion module (MBFM). The AIEM extracts spatial and spectral features from input images and captures the correlations between features. The MBFM can efficiently integrate information from the AIEM and improve MSBANet context awareness. We design a hybrid loss function that enhances the ability of the fusion network to store spectral and texture details. In qualitative and quantitative experimental studies on four datasets, MSBANet outperformed state-of-the-art pansharpening techniques. The code will be released. © 2024 IEEE.

关键词： Data mining

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Voice Transmission Enhancing Model on Wireless Mesh Networks

Voice Transmission Enhancing Model on Wireless Mesh Networks

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IEEE International Conference on communications (ICC)

作者： S. Jung S. Hong K. Kim J. Jee E. Kim Dept. of Electrical and Computer Engineering Mobile Systems Design Laboratory Stony Brook University Suny Stony Brook NY Mobile Communication Standardization Research Team Electronics and Telecommunications Research Institute Daejeon South Korea Mobile Communication Standardization Research Team Electronics and Telecommunications Research Institute Daejeon KOREA

This paper initially shows ROHC and packet aggregation significantly improve the number of successful voice calls. However, the improvement does not include processor's processing overhead, which is identified by measuring ROHC processing time from Intel Pentium 4 and RouterBOARD, and applying the results into NS-2 simulations. Simulation results indicate the number of successful voice calls is seriously affected by the processing overhead. For the solution of the processing limitation, we propose a hardware model of the two algorithms and numerically analyze the model. Simulation results show the hardware model makes the number of successful voice calls approach the ideal (no-delay) case, and the numerical model exactly characterizes the hardware behaviors.

关键词： Wireless mesh networks Numerical models Propagation losses Robustness Hardware design languages Time measurement Power system modeling Traffic control Telecommunication traffic Spread spectrum communication

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