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Multidimensional fourier transforms by systolic architectures

Journal of VLSI Signal Processing 1992年第4期4卷 343-354页

作者： Roziner, T.D. Karpovsky, M.G. Research Laboratory for Design and Testing of Computers and Communication Systems Department of Computer and Systems Engineering Boston University Boston 02215 Massachusetts 44 Cummington Street United States

In this paper, time-efficient systolic and semi-systolic architectures for the implementation of multidimensional DFTs are proposed that allow modularity and easy expansibility while keeping throughput independent of the dimension of the DFT. We shall call an array semi-systolic if the input data is to be preloaded into every cell of the array or if the output data can be calculated not only in the boundary cells of the array. DFT algorithms are represented by FORTRAN-like code, in order to explicitly display the suggested rotational transformations in the index space. After the transformation, multidimensional DFT algorithm can be mapped onto a systolic structure. The area-time² complexity of the proposed design is within log k factor of the lower bound for a k-point DFT (AT²=Ω(k² log²k)), i.e. equals 0(k² log³k)=0(N^{2 M} log³N) for k=N^{2 M} point DFT;A is the area complexity and T is the system throughput. © 1992 Kluwer Academic Publishers.

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Multidimensional Fourier transforms by systolic architectures

Multidimensional Fourier transforms by systolic architecture...

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International Conference on Databases, Parallel Architectures and Their Applications

作者： T.D. Roziner Research Laboratory for Design and Testing of Computer and Communication Systems College of Engineering Boston University Boston MA USA

A method of formal transformation of a multidimensional DFT (discrete Fourier transform) algorithm to a form suitable for implementation with a systolic macropipeline is discussed. The suggested transformation of the original form of the DFT algorithm consists of one or several rotationlike transforms applied to the index set. The resulting 'completely systolized' form of the algorithm makes it possible to implement the N/sup M/-point (m-dimensional) DFT with a macropipeline containing M or (M-1) cascaded systolic/semisystolic arrays. Each array is an M-dimensional hypercube of the processing elements (PEs) of the multiply-add type; the internal structure of PEs in different arrays is slightly different. For given values of N and M, several design options exist, with hardware complexity of about the same value. The proposed systolic architecture makes it possible to obtain the throughput of N (one set of spectrum values every N array clocks) for any number of dimensions M.< >

关键词： Multidimensional systems Fourier transforms Discrete Fourier transforms Throughput Very large scale integration Systolic arrays design for testability Circuits Computer architecture Laboratories

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Board-level diagnosis by signature analysis

Board-level diagnosis by signature analysis

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IEEE International Test Conference

作者： M.G. Karpovsky P. Nagvajara Research Laboratory for Design and Testing of Computer and Communication Systems Computer and Communication Systems Computer and Communication Systems Department of Electrical Computer and System Engineering Boston University Boston MA USA

Board-level diagnostic techniques by signature analysis based on single-error-correcting Hamming codes over GF(2/sup M/) (where M is the number of outputs per chip) are presented. Two techniques are considered: the space-time compressor technique for the case when responses from N chips on the board are wired to the compressor; and the time compressor technique for the case when test responses from each chip are transferred to the compressor via system bus. Assuming a single-faulty-chip model, a faulty chip on the board under test is located by an analysis of the relationship between the distortions in the obtained signatures. Both techniques for board-level diagnosis require less hardware than the straightforward diagnostic techniques using a built-in signature analyzer for every chip or selective testing of each chip via the system bus, hence offering an efficient approach for a design of a built-in-self-test board for for manufacturing testing.< >

关键词： System testing System buses Hardware Built-in self-test Automatic testing Pattern analysis Fault diagnosis Laboratories design engineering systems engineering and theory

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Efficient test generation for built-in self-test boundary-scan template

Efficient test generation for built-in self-test boundary-sc...

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1991 IEEE VLSI Test Symposium: Chip-to-System Test Concerns for the 90''s, VTEST 1991

作者： Nagvajara, P. Karpovsky, M.G. Levitin, L.B. Dept. of Electr. and Comput. Eng. Drexel Univ. PhiladelphiaPA United States Research Laboratory for Design and Testing of Computer and Communication Systems Department of Electrical Computer and System Engineering Boston University United States

An analysis and design of a pseudorandom pattern generator, (PRPG), based on a linear recurrence, for built-in self-test (BIST) boundary scan design is presented. The authors present for the case when r≥s, a design of an s-stage PRPG capable of producing 2s-1 distinct r-bit patterns within 2s-1 clock pulses independent of the hardware realization of the PRPG. For the case when rr distinct r-bit patterns and the expected number T(N) of distinct patterns given a number N of clock pulses were presented. The proposed theoretical average N(T) was shown to be close to the experimental average values Nex(T). Hence, the value N(T) or T(N) can be used as a benchmark for evaluating the efficiency of a BIST boundary scan test generation. © 1991 IEEE.

关键词： Built-in self test

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Efficient test generation for built-in self-test boundary-scan template

Efficient test generation for built-in self-test boundary-sc...

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VLSI Test Symposium

作者： P. Nagvajara M.G. Karpovsky L.B. Levitin Department of Electrical and Computer Engineering Drexel University Philadelphia PA USA Research Laboratory for Design and Testing of Computer and Communication Systems Department of Electrical Computer and System Engineering Boston University Boston MA USA

关键词： Automatic testing Built-in self-test Circuit testing Clocks Test pattern generators Pulse generation Pattern analysis Laboratories System testing design engineering

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Computation of electric fields from electric charges. Coulomb's law or poisson's equation

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Computer Applications in Engineering Education 1993年第5期1卷 445-445页

作者： Fazarine, Z. Hewlett-Packard Laboratories In 1965 he joined Hewlett-Packard Laboratories in Palo Alto where he conducted research in the areas of circuits and systems and solid-state devices. As a laboratory director Dr. Fazarinc has managed research in the areas of measurement computation data communication and design tools. Dr. Fazarinc has taught at Stanford University since 1972 as a consulting professor. His most recent research centered on the use of computers for building an intuitive understanding of concepts in physics. He continues to pursue this activity as part of his teaching and consulting.

Coulomb's Law and Poisson's equation are revisited and compared as algorithms for computer evaluation of electric force fields. In the course of this examination we point to the danger of applying physical laws measured in three-dimensional space to spaces of other dimensionalities. The algorithms based on Coulomb's Law and on Poisson's equation are cast in C-language and are illustrated with a two-dimensional example.

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Discretization of partial differential equations for computer evaluation

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Computer Applications in Engineering Education 1992年第1期1卷 73-73页

作者： Fazarine, Z. Senior Science Advisor to Hewlett-Packard Laboratories and Consulting Professor Stanford University Stanford California In 1965 he joined Hewlett-Packard Laboratories in Palo Alto where he conducted research in the areas of circuits and systems and solid-state devices. As a laboratory director. Dr. Fazarinc has managed research in the areas of measurement computation data communication and design tools. Dr. Fazarinc has taught at Stanford University since 1972 as a consulting professor. His most recent research centered on the use of computers for building an intuitive understanding of concepts in physics. He continues to pursue this activity as part of his teaching and consulting.

Physics described by partial differential equations is difficult to visualize. Computer solutions of such equations supported with dynamic graphic displays are therefore of high interest to educators and scientists [1]. Translation of partial differential equations into formats understood by computers is beset with complexity and pitfalls. This article explores a direct method for deriving the relevant algorithms from physics itself and illustrates the approach with examples in propagation and diffusion. The resulting algorithms are cast into C-language.

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ARCTIC TRAFFICABILITY PROGRAM - A REVIEW

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NAVAL ENGINEERS JOURNAL 1984年第3期96卷 169-175页

作者： VOELKER, R GLEN, IF SEIBOLD, F BAYLY, I Richard Voelker:is Vice President of ARCTEC Incorporated a firm specializing in cold regions technology. He has been responsible for the management of thePolarClass Traffic-ability Program since its inception and annually participates in the field data collection in the Arctic. His prior experience includes positions with the U.S. Coast Guard in the icebreaker design project the Military Sealift Command and at Newport News Shipbuilding. He is a graduate of N. Y.S. Maritime College and has a MS degree from the University of Michigan. I.F. Glen:received his professional degrees in naval architecture from the Royal Naval Engineering College Manadon Plymouth and RN College Greenwich London entering the Royal Corps of Naval Constructors in 1967. After serving as a Constructor Lieutenant in the Royal Navy's Far East Fleet for a short period he joined the Polaris submarine project team in Bath England in 1968. In 1971 he was seconded to the Canadian Department of National Defense in Ottawa as a Constructor Lieutenant Commander under NATO exchange arrangements where he had responsibilities initially for conventional submarines and latterly for computer aided conceptual design. He ventured to Bath England in 1974 and joined Forward Design Group. In 1975 he took a position as a civilian engineer in the Canadian Defense Department and was Head of Hull Systems Engineering from 1977 to 1979. He joined ARCTEC CANADA LIMITED in 1980 and in addition to managing ice model testing projects and full scale trials has specialized in structural response of ships to ice impact. He headed ARCTEC's Kanata Laboratory from 1981 to 1983 when he was promoted to president. Frederick Seibold:is a research program manager with the Maritime Administration's Office of Advanced Ship Development and Technology. He is responsible for the marine science program which includes research in the areas of ship powering structures and propeller performance and Arctic technology. Mr. Seibold has been employed by Mar Ad since 1961 having hel

This paper describes a multiyear program to make an operational assessment on the feasibility of a year-round Arctic marine transportation system to serve Alaska. Specifically, the three objectives were to: collect meteorological and ice data along potential marine routes; instrument the hull and propulsion machinery to improve design critera for ice-worthy ships; and demonstrate that ships can operate in midwinter Alaskan Arctic ice conditions. The U.S. Coast Guard's Polar class icebreakers were used to make the operational assessment by annually extending the route northward and by operating throughout the winter season. This paper reviews some of the operational and technical achievements to date, as well as plans for future Arctic deployments.

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