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23rd USENIX Conference on File and Storage Technologies, FAST 2025

作者： Li, Changlong Zhu, Zongwei Wang, Chao Liu, Fangming Xu, Fei Sha, Edwin H.-M. Zhou, Xuehai School of Computer Science and Technology East China Normal University China Jianghuai Advance Technology Center Hefei230026 China MoE Engineering Research Center of Hardware/Software Co-Design Technology and Application China School of Software Engineering University of Science and Technology of China Hefei230026 China Suzhou Institute for Advanced Research University of Science and Technology of China Suzhou215123 China Huazhong University of Science and Technology China Peng Cheng Laboratory China

ISBN: (纸本)9781939133458

In mobile systems, memory can be compressed page-by-page to save space. This approach is widely adopted because memory data is accessed by page. However, this paper shows that the system response speed is significantly limited by page-grained compression. In this paper, we observe that approximately a quarter of anonymous memory pages are highly correlated, even though the association is implicit. Inspired by this, we propose Archer, an association-rule-aware memory compression framework in mobile systems. Archer demonstrates that memory in mobile devices should be compressed using flexible granularity, rather than relying solely on traditional page compression. To further integrate association-rule mining techniques into system design, we redesign the LRU mechanism and propose an adaptive memory compression region. Experimental results show that the average app launching speed is 1.55x faster when enabling Archer, and the average photographic speed and frame rate increase by 1.42x and 1.31x, respectively, compared to the state-of-the-art. © 2025 FAST. All Rights Reserved.

关键词： Portable equipment

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Transparent random access memory testing for pattern sensitive faults

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JOURNAL OF ELECTRONIC testing-THEORY AND APPLICATIONS 1996年第3期9卷 251-266页

作者： Karpovsky, MG Yarmolik, VN Research Laboratory of Design and Testing of Computer Hardware Department of Electrical Computer and Systems Engineering Boston University Boston USA

This paper presents a new methodology for RAM testing based on the PS(n, k) fault model (the k out of n pattern sensitive fault model). According to this model the contents of any memory cell which belongs to an n-bit memory block, or the ability to change the contents, is influenced by the contents of any k-1 cells from this block. The proposed methodology is a transparent BIST technique, which can be efficiently combined with on-line error detection. This approach preserves the initial contents of the memory after the rest and provides for a high fault coverage for traditional fault and error models, as well as for pattern sensitive faults. This paper includes the investigation of testing approaches based on transparent pseudoexhaustive testing and its approximations by deterministic and pseudorandom circular tests. The proposed methodology can be used for periodic and manufacturing testing and require lower hardware and time overheads than the standard approaches.

关键词： random access memory memory testing exhaustive memory testing transparent memory testing built-in self-test pseudo-exhaustive memory testing pattern sensitive faults signature analysis

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Prophet: SSD Failure Analysis and Prediction Guided by Flash Reliability Characteristics in Data Centers

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IEEE Transactions on computers 2025年

作者： Song, Yunpeng Liang, Yujiong Liu, Jialin Shi, Liang East China Normal University MoE Engineering Research Center of Software/Hardware Co-Design Technology and Application Shanghai China East China Normal University School of Computer Science and Technology Shanghai China Huazhong University of Science and Technology Wuhan National Laboratory for Optoelectronics Wuhan China

Solid-state drives (SSDs) are massively deployed in various fields, especially in data centers, for their excellent cost-effectiveness. However, SSDs may fail due to their imperfect manufacturing processes, resulting in system-level failures and even downtime in data centers. This makes SSD failure prediction critical. Current studies focus on dealing with data missing, numerical normalization, and other statistical issues in using machine learning methods, but the consideration of the reliability characteristics of the underlying flash media of SSDs and the timeliness (time duration between predicted failure and real failure) of SSD failure prediction result is missing. In this work, we study the failure characteristics of over 200,000 drives from industry data centers over a 4-year period, as well as daily data. The relationship between SSD attribute values and failures is first investigated. Then, we analyzed the SSD failure characteristics from several aspects (causes, differences between failures, and timeliness of prediction results) relying on flash reliability characteristics. Based on these, a novel SSD failure prediction method (Prophet) is proposed. Specifically, Prophet contains the following two components. First, to cope with the differences between failures, a diff-state method is proposed for differential machine learning modeling of SSDs in different "States". We define the "State" of an SSD, which represents the range of values in which the SSD currently lies in terms of some key attributes. Through flash reliability characteristics, we distinguish between different failures before training the model to obtain accurate predictions of different failure behaviors. Second, a recovery period method is proposed to enhance the timeliness of SSD failure prediction result by designing the sample selection method. The enhanced timeliness can be utilized by operations personnel to handle failed SSDs, such as replacement and repair. The evaluation results of

关键词： Failure rate

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Exhaustive and near-exhaustive memory testing techniques and their BIST implementations

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JOURNAL OF ELECTRONIC testing-THEORY AND APPLICATIONS 1997年第3期10卷 215-229页

作者： Das, D Karpovsky, M Research Lab. on Design and Testing of Computer Hardware Boston University Boston

In this work we investigate the problem of detection and location of single and unlinked multiple k-coupling faults in n x 1 random-access memories (RAMs). This fault model covers all crosstalks between any k cells in n x 1 RAMs. The problem of memory testing has been reduced to the problem of the generation of (n, k - 1)-exhaustive backgrounds. We have obtained practical test lengths, for a memory size around 1 M, for detecting up to 6-couplings by exhaustive tests and up to 9-couplings by near-exhaustive tests. The best known test algorithms up to now provide for the detection of 5-couplings only in a 1 M memory, using exhaustive tests. Beyond these parameters, test lengths were impractical. Furthermore, our method for generation of (n, k - 1)-exhaustive backgrounds yields short test lengths giving rise to considerably shorter testing times than the present most efficient tests for large n and for k greater than 3. Our test lengths are 50% shorter than other methods for the case of detecting up to 5-couplings in a 1 Mbit RAM. The systematic nature of both our tests enables us to use a built-in self-test (BIST) scheme, for RAMs, with low hardware overhead. For a 1 Mbit memory, the BIST area overhead for the detection of 5-couplings is less than 1% for SRAM and 6.8% for a DRAM. For the detection of 9-couplings with 99% or higher probability, the BIST area overhead is less than 0.2% for SRAM and 1.5% for DRAM.

关键词： memory testing pattern sensitive faults built-in self-test exhaustive codes near-exhaustive codes

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GIRP: Energy-Efficient QoS-Oriented Microservice Resource Provisioning via Multi-Objective Multi-Task Reinforcement Learning

引用

IEEE Transactions on Mobile Computing 2025年

作者： Yuan, Honggang Wang, Ting Fu, Min Shi, Yuanming East China Normal University MoE Engineering Research Center of Software/Hardware Co-design Technology and Application Shanghai Key Laboratory of Trustworthy Computing Shanghai200062 China National University of Singapore Department of Electrical and Computer Engineering 117583 Singapore ShanghaiTech University School of Information Science and Technology Shanghai201210 China

Microservice architecture has revolutionized web service development by facilitating loosely coupled and independently developable components distributed as containers or virtual machines. While existing studies emphasize end-to-end latency, this paper investigates energy-efficient quality-of-service (QoS)-oriented microservice provisioning, focusing on both QoS satisfaction and power consumption (PC) conservation. We propose the Green and Intelligent Resource Provision (GIRP) architecture, integrating a data-driven energy-latency-aware resource allocation and scheduling manager to balance latency and PC. To reconcile the trade-offs involved, a dual-objective optimization problem is formulated to minimize latency and energy use by selecting proper servers, allocating CPU cores, and determining service replicas. To address challenges with discrete variables, dual objectives, and implicit mappings, we leverage a model-free deep deterministic policy gradient-based reinforcement learning algorithm. Specifically, we develop a multi-task agent via the Multi-gate Mixture-of-Experts model to simultaneously make two separate actions regarding CPU core numbers and service replica numbers, followed by a single-task agent to determine service scheduling. Extensive experiments on the DeathStarBenchmark testbed validate GIRP's effectiveness, demonstrating approximately 52% resource savings and a 43% reduction in PC compared to leading methods like Sinan, Firm, and heuristic-based algorithms. These results highlight GIRP's capability to optimize microservice orchestration by balancing end-to-end latency and power efficiency. © 2025 IEEE. All rights reserved.

关键词： Quality of service

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Archer: adaptive memory compression with page-association-rule awareness for high-speed response of mobile devices 25

Archer: adaptive memory compression with page-association-ru...

引用

Proceedings of the 23rd USENIX Conference on File and Storage Technologies

作者： Changlong Li Zongwei Zhu Chao Wang Fangming Liu Fei Xu Edwin H.-M. Sha Xuehai Zhou School of Computer Science and Technology East China Normal University and Jianghuai Advance Technology Center Hefei China and MoE Engineering Research Center of Hardware/Software Co-Design Technology and Application School of Software Engineering University of Science and Technology of China Hefei China and Suzhou Institute for Advanced Research University of Science and Technology of China Suzhou China Huazhong University of Science and Technology and Peng Cheng Laboratory School of Computer Science and Technology East China Normal University

ISBN: (纸本)9781939133458

In mobile systems, memory can be compressed page-by-page to save space. This approach is widely adopted because memory data is accessed by page. However, this paper shows that the system response speed is significantly limited by page-grained compression. In this paper, we observe that approximately a quarter of anonymous memory pages are highly correlated, even though the association is implicit. Inspired by this, we propose Archer, an association-rule-aware memory compression framework in mobile systems. Archer demonstrates that memory in mobile devices should be compressed using flexible granularity, rather than relying solely on traditional page compression. To further integrate associationrule mining techniques into system design, we redesign the LRU mechanism and propose an adaptive memory compression region. Experimental results show that the average app launching speed is 1.55x faster when enabling Archer, and the average photographic speed and frame rate increase by 1.42x and 1.31x, respectively, compared to the state-of-the-art.

关键词：

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ConZone: A Zoned Flash Storage Emulator for Consumer Devices

ConZone: A Zoned Flash Storage Emulator for Consumer Devices

引用

design, Automation and Test in Europe Conference and Exhibition

作者： Dingcui Yu Jialin Liu Yumiao Zhao Wentong Li Ziang Huang Zonghuan Yan Mengyang Ma Liang Shi MoE Engineering Research Center of Software/Hardware Co-Design Technology and Application East China Normal University Shanghai China College of Computer Science and Technology East China Normal University Shanghai China Software Engineering Institute East China Normal University Shanghai China Wuhan National Laboratory for Optoelectronics Huazhong University of Science and Technology Wuhan China

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Considering the potential benefits to lifespan and performance, zoned flash storage is expected to be incorporated into the next generation of consumer devices. However, due to the limited volatile cache and heterogeneous flash cells of consumer-grade flash storage, adopting a zone abstraction requires additional internal hardware design to maximize its benefits. To understand and efficiently improve the hardware design on consumer-grade zoned flash storage, we present ConZone—the first emulator tailored to the characteristics of consumer-grade zoned flash storage. Users can explore the internal architecture and management strategies of consumer-grade zoned flash storage and integrate the optimization with software. We validate the accuracy of ConZone by realizing a hardware architecture for consumer-grade zoned flash storage and comparing it with the state-of-the-art. We also make a case study for read performance research with ConZone to explore the design of mapping mechanisms and cache management strategies.

关键词： Performance evaluation Accuracy Europe computer architecture hardware Software Planning Optimization Next generation networking

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SAFL: Structure-Aware Personalized Federated Learning via Client-Specific Clustering and SCSI-Guided Model Pruning

arXiv

引用

arXiv 2025年

作者： Li, Nan Wang, Xiaolu Du, Xiao Cai, Puyu Wang, Ting Engineering Research Center of Software/Hardware Co-Design Technology and Application Ministry of Education the Shangh ai Key Laboratory of Trustworthy Computing East China Normal University Shanghai200062 China Software Engineering Institute East China Normal University Shanghai200050 China Computer Science Department New York University New YorkNY10012 United States

Federated Learning (FL) enables clients to collaboratively train machine learning models without sharing local data, preserving privacy in diverse environments. While traditional FL approaches preserve privacy, they often struggle with high computational and communication overhead. To address these issues, model pruning is introduced as a strategy to streamline computations. However, existing pruning methods, when applied solely based on local data, often produce sub-models that inadequately reflect clients’ specific tasks due to data insufficiency. To overcome these challenges, this paper introduces SAFL (Structure-Aware Federated Learning), a novel framework that enhances personalized federated learning through client-specific clustering and Similar Client Structure Information (SCSI)-guided model pruning. SAFL employs a two-stage process: initially, it groups clients based on data similarities and uses aggregated pruning criteria to guide the pruning process, facilitating the identification of optimal sub-models. Subsequently, clients train these pruned models and engage in server-based aggregation, ensuring tailored and efficient models for each client. This method significantly reduces computational overhead while improving inference accuracy. Extensive experiments demonstrate that SAFL markedly diminishes model size and improves performance, making it highly effective in federated environments characterized by heterogeneous data. Copyright © 2025, The Authors. All rights reserved.

关键词： Federated learning

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Built-in self-diagnostic by space-time compression of test responses

Built-in self-diagnostic by space-time compression of test r...

引用

1992 IEEE VLSI Test Symposium, VLSI 1992

作者： Karpovsky, M.G. Chaudhry, S.M. Research Laboratory of Design and Testing of Computer Hardware Department of Electrical Computer and Systems Engineering Boston University BostonMA02215 United States

ISBN: (纸本)0780306236

Presents two different methodologies for built-in self-diagnostic of boards and systems by space-time compression of test responses. The first method, soft decision, uses nonbinary multiple error-correcting codes to obtain space-time signatures. These obtained signatures and the corresponding precomputed references are compared and magnitudes of distortions in signatures are analyzed to identify faulty components. The second method, hard decision, makes use of the information indicating whether the corresponding signatures are distorted or not. Both approaches show considerable savings in hardware overheads when compared with a straightforward approach where a separate signature is required for every component. A transition from the soft to hard decision approach results in an increase in the number of signatures required for diagnostic but at the same time it results in a decrease in the complexity of a fault locating algorithm. Results pertaining to VLSI implementations are presented where the hardware overhead is estimated in terms of two-input equivalent gates. © 1992 IEEE.

关键词： Data compression

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Detection and location of given sets of errors by nonbinary linear codes 1st

引用

1st French-Israeli Workshop on Algebraic Coding, 1993

作者： Karpovsky, Mark G. Chaudhry, Saeed M. Levitin, Lev B. Moraga, Claudio Research Laboratory of Design and Testing of Computer Hardware Department of Electrical Computer and Systems Engineering Boston University BostonMA02215 United States Department of Computer Science University of Dortmund Dortmund 504600 Germany

ISBN: (纸本)9783540578437

The problem of constructing codes capable of detection and location of a given set of errors is considered. Lower and upper bounds on a number of redundant symbols for an arbitrary set of errors are derived. These codes can be used for error detection and identification of faulty processing elements in multiprocessor systems. To this end, new classes of codes for several types of error sets such as stars, trees and FFTs meshes are presented. The concepts of strong and weak diagnostics (SD and WD, respectively) are introduced and discussed. © 1994, Springer Verlag. All rights reserved.

关键词： Location

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