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International Symposium on Fault-Tolerant Computing (FTCS)

作者： M.G. Karpovsky S.M. Chaudhry L.B. Levitin Research Laboratory of Design and Testing of Computer Hardware Department of Electrical Computer and Systems Engineering Boston University Boston MA USA

A framework, based on nonbinary multiple error correcting codes, for built-in self-diagnostics is presented. Novel space-time compressors are proposed for test response compression and fault diagnosis. Fault-detecting and locating capabilities for space-time compressors are analyzed in the case when nonbinary Reed-Solomon codes are used. Fault-masking and diagnosis probabilities for the chip-independent error model are estimated. For this error-model, the fault-masking probabilities are analyzed using the weight distributions of Reed-Solomon codes.< >

关键词： Circuit faults Compressors Fault diagnosis Automatic testing System testing Built-in self-test Electrical fault detection Fault detection Error correction codes Laboratories

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Built-in self-diagnostic by space-time compression of test responses

Built-in self-diagnostic by space-time compression of test r...

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VLSI Test Symposium

作者： M.G. Karpovsky S.M. Chaudhry Research Laboratory of Design and Testing of Computer Hardware Department of Electrical Computer and Systems Engineering Boston University Boston MA USA

Presents two different methodologies for built-in self-diagnostic of boards and systems by space-time compression of test responses. The first method, soft decision, uses nonbinary multiple error-correcting codes to obtain space-time signatures. These obtained signatures and the corresponding precomputed references are compared and magnitudes of distortions in signatures are analyzed to identify faulty components. The second method, hard decision, makes use of the information indicating whether the corresponding signatures are distorted or not. Both approaches show considerable savings in hardware overheads when compared with a straightforward approach where a separate signature is required for every component. A transition from the soft to hard decision approach results in an increase in the number of signatures required for diagnostic but at the same time it results in a decrease in the complexity of a fault locating algorithm. Results pertaining to VLSI implementations are presented where the hardware overhead is estimated in terms of two-input equivalent gates.< >

关键词： Automatic testing Fault diagnosis System testing hardware Error correction codes Built-in self-test Information analysis Laboratories design engineering Systems engineering and theory

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Identification of faulty processing elements by space-time compression of test responses

Identification of faulty processing elements by space-time c...

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IEEE International Test Conference

作者： M.G. Karpovsky L.B. Levitin F.S. Vainstein Research Laboratory of Design and Testing of Computer Hardware Department of Electrical Computer and Systems Engineering Boston University Boston MA USA

A novel approach to the identification of a faulty processing element, based on an analysis of the compressed response of the system, is proposed. The test response is compressed first in space and then in time, and a faulty processing element is identified by a hard-decision decoding of the corresponding space-time signature. The overhead analysis and the solution for the hardware minimization problem are presented for several important classes of systems. The proposed method results in considerable hardware savings.< >

关键词： Fault diagnosis System testing hardware design engineering Decoding Laboratories Systems engineering and theory Educational institutions Vectors System buses

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Multidimensional fourier transforms by systolic architectures

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Journal of VLSI Signal Processing 1992年第4期4卷 343-354页

作者： Roziner, T.D. Karpovsky, M.G. Research Laboratory for Design and Testing of Computers and Communication Systems Department of Computer and Systems Engineering Boston University Boston 02215 Massachusetts 44 Cummington Street United States

In this paper, time-efficient systolic and semi-systolic architectures for the implementation of multidimensional DFTs are proposed that allow modularity and easy expansibility while keeping throughput independent of the dimension of the DFT. We shall call an array semi-systolic if the input data is to be preloaded into every cell of the array or if the output data can be calculated not only in the boundary cells of the array. DFT algorithms are represented by FORTRAN-like code, in order to explicitly display the suggested rotational transformations in the index space. After the transformation, multidimensional DFT algorithm can be mapped onto a systolic structure. The area-time² complexity of the proposed design is within log k factor of the lower bound for a k-point DFT (AT²=Ω(k² log²k)), i.e. equals 0(k² log³k)=0(N^{2 M} log³N) for k=N^{2 M} point DFT;A is the area complexity and T is the system throughput. © 1992 Kluwer Academic Publishers.

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Efficient test generation for built-in self-test boundary-scan template

Efficient test generation for built-in self-test boundary-sc...

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1991 IEEE VLSI Test Symposium: Chip-to-System Test Concerns for the 90''s, VTEST 1991

作者： Nagvajara, P. Karpovsky, M.G. Levitin, L.B. Dept. of Electr. and Comput. Eng. Drexel Univ. PhiladelphiaPA United States Research Laboratory for Design and Testing of Computer and Communication Systems Department of Electrical Computer and System Engineering Boston University United States

An analysis and design of a pseudorandom pattern generator, (PRPG), based on a linear recurrence, for built-in self-test (BIST) boundary scan design is presented. The authors present for the case when r≥s, a design of an s-stage PRPG capable of producing 2s-1 distinct r-bit patterns within 2s-1 clock pulses independent of the hardware realization of the PRPG. For the case when rr distinct r-bit patterns and the expected number T(N) of distinct patterns given a number N of clock pulses were presented. The proposed theoretical average N(T) was shown to be close to the experimental average values Nex(T). Hence, the value N(T) or T(N) can be used as a benchmark for evaluating the efficiency of a BIST boundary scan test generation. © 1991 IEEE.

关键词： Built-in self test

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Multidimensional Fourier transforms by systolic architectures

Multidimensional Fourier transforms by systolic architecture...

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International Conference on Databases, Parallel Architectures and Their Applications

作者： T.D. Roziner Research Laboratory for Design and Testing of Computer and Communication Systems College of Engineering Boston University Boston MA USA

A method of formal transformation of a multidimensional DFT (discrete Fourier transform) algorithm to a form suitable for implementation with a systolic macropipeline is discussed. The suggested transformation of the original form of the DFT algorithm consists of one or several rotationlike transforms applied to the index set. The resulting 'completely systolized' form of the algorithm makes it possible to implement the N/sup M/-point (m-dimensional) DFT with a macropipeline containing M or (M-1) cascaded systolic/semisystolic arrays. Each array is an M-dimensional hypercube of the processing elements (PEs) of the multiply-add type; the internal structure of PEs in different arrays is slightly different. For given values of N and M, several design options exist, with hardware complexity of about the same value. The proposed systolic architecture makes it possible to obtain the throughput of N (one set of spectrum values every N array clocks) for any number of dimensions M.< >

关键词： Multidimensional systems Fourier transforms Discrete Fourier transforms Throughput Very large scale integration Systolic arrays design for testability Circuits computer architecture Laboratories

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CRFs for Digital Signature and NIZK Proof System in Web Services 1

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22nd International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2022

作者： Kang, Burong Zhang, Lei Yang, Yafang Meng, Xinyu Engineering Research Center of Software/Hardware Co-design Technology and Application Ministry of Education East China Normal University Shanghai200062 China Science and Technology on Communication Security Laboratory Sichuan610041 China Research Institute of China Telecom Corporation Limited Shanghai200062 China School of Computer Science Fudan University Shanghai200433 China

ISBN: (数字)9783031226779

ISBN: (纸本)9783031226762

Web services are service-oriented computing technology which allows computers running different operating domains to access and share each other’s databases. Each web service is an application (like online business) which may require the private information of users. Thus, it will be important to preserve these web users’ individual privacy. The traditional approaches to achieve this goal in web security is to use the cryptographic technologies, such as digital signature, NIZK proof system. Whereas, some recent research results indicate that these cryptographic technologies may suffer from the algorithm substitution attack (ASA). ASA means that the cryptographic technology would be embedded some backdoor in the process of its implementation by the attacker, and with the backdoor information the attacker can steal the user’s private information. To address this problem, the concept of cryptographic reverse firewall (CRF) has been introduced, which could sanitize the messages inputting and outputting the user’s computer. In this paper, we construct the CRFs for the efficient Pointcheval-Sanders (PS) signature as well as the NIZK proof system. © 2023, Springer Nature Switzerland AG.

关键词： Web services

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Board-level diagnosis by signature analysis

Board-level diagnosis by signature analysis

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IEEE International Test Conference

作者： M.G. Karpovsky P. Nagvajara Research Laboratory for Design and Testing of Computer and Communication Systems Computer and Communication Systems Computer and Communication Systems Department of Electrical Computer and System Engineering Boston University Boston MA USA

Board-level diagnostic techniques by signature analysis based on single-error-correcting Hamming codes over GF(2/sup M/) (where M is the number of outputs per chip) are presented. Two techniques are considered: the space-time compressor technique for the case when responses from N chips on the board are wired to the compressor; and the time compressor technique for the case when test responses from each chip are transferred to the compressor via system bus. Assuming a single-faulty-chip model, a faulty chip on the board under test is located by an analysis of the relationship between the distortions in the obtained signatures. Both techniques for board-level diagnosis require less hardware than the straightforward diagnostic techniques using a built-in signature analyzer for every chip or selective testing of each chip via the system bus, hence offering an efficient approach for a design of a built-in-self-test board for for manufacturing testing.< >

关键词： System testing System buses hardware Built-in self-test Automatic testing Pattern analysis Fault diagnosis Laboratories design engineering Systems engineering and theory

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SLSNet: Weakly-Supervised Skin Lesion Segmentation Network with Self-attentions 20th

SLSNet: Weakly-Supervised Skin Lesion Segmentation Network w...

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20th Pacific Rim International Conference on Artificial Intelligence, PRICAI 2023

作者： Pei, Songwen Huang, Junjie School of Optical-Electrical and Computer Engineering University of Shanghai for Science and Technology Shanghai200093 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing100190 China Engineering Research Center of Software/Hardware Co-design Technology and Application Ministry of Education East China Normal University Shanghai200062 China

ISBN: (纸本)9789819970247

computer-aided skin lesion segmentation with high precision is crucial to diagnose skin cancers in the early stage. However, the lack of pixel-level labels makes the skin lesion segmentation tasks challenging. To tackle this problem, a new weakly-supervised skin lesion segmentation network with self-attentions named SLSNet is proposed. SLSNet contains two modules and uses image-level labels as supervision information. One module named Intra-image Self-attention Seed Expansion (ISE) digs intra-image self-attentions with an expansion loss and a confidence loss to expand seed areas. The other module named Inter-image Affinity-based Noise Suppression (IAS) suppresses the noise pixels in attention maps via inter-image correlations. Extensive experiments conducted on ISIC-2017 dataset show that SLSNet achieves relatively high performance while reducing human labeling efforts. © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd 2024.

关键词： Expansion

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Efficient test generation for built-in self-test boundary-scan template

Efficient test generation for built-in self-test boundary-sc...

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VLSI Test Symposium

作者： P. Nagvajara M.G. Karpovsky L.B. Levitin Department of Electrical and Computer Engineering Drexel University Philadelphia PA USA Research Laboratory for Design and Testing of Computer and Communication Systems Department of Electrical Computer and System Engineering Boston University Boston MA USA

关键词： Automatic testing Built-in self-test Circuit testing Clocks Test pattern generators Pulse generation Pattern analysis Laboratories System testing design engineering

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