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检索条件"机构=Research and Development Center of System Simulation Technology"

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Integration Friendly Dual Metal Gate technology Using Dual Thickness Metal Inserted Poly-Si Stacks (DT-MIPS)

Integration Friendly Dual Metal Gate Technology Using Dual T...

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Symposium on VLSI technology

作者： Hyung-Suk Jung Sung Kee Han Hajin Lim Yun Ki Choi Cheol-kyu Lee Mong sub Lee Young-sub You Youngsu Chung Jong-bong Park Eun Ha Lee Hion Suck Baik Jong-Ho Lee Nae-In Lee Ho-Kyu Kang Advanced Process Development Team System LSI Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Semiconductor Research and Development Center Memory Division Samsung Electronics Company Limited South Korea AE Center Samsung Advanced Institute of Technology Gyeonggi South Korea

ISBN: (纸本)9784900784031;4900784036

We have successfully developed integration friendly dual metal gate process utilizing a dual thickness metal inserted poly-Si stacks (DT-MIPS) structure; poly-Si/TaN/HfON stacks for nMOS and poly-Si/capping metal layer(c-ML)/AlO x /TaN/HfON stacks for pMOS. First, in spite of different metal thickness on n/pMOS, a high-selectivity gate etch process can completely remove metal and HfON layers from the S/D active regions with negligible Si recess in both n/pMOS. Consequently, in both short and long channel devices, n/pMOS V th values of ~plusmn0.35 V are obtained without counter channel doping. Moreover, excellent drive currents (620/250 muA/um for n/pMOS at I off =20 pA/um and V dd =1.2 V) are obtained without using any mobility enhancement technique. Finally, we confirm that the estimated operation voltages for 10 years lifetime for both nMOS PBTI and pMOS NBTI are well beyond the 1.2 V.

关键词： MOS devices Etching Fabrication CMOS process Large scale integration research and development Counting circuits Doping Life estimation Lifetime estimation

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Long duration real-time observation of Irrawaddy dolphins in Chilika lagoon

Long duration real-time observation of Irrawaddy dolphins in...

引用

2007 OCEANS, vol.3

作者： T. Inoue T. Ura H. Sugimatsu T. Sakamaki J. Kojima R. Bahl S. Panda M. Khan B. K. Behera S. K. Behera H. Takahashi S. Kar C. Kar Ura Laboratory Underwater Technology Research Center Institute of Industrial Science University of Tokyo Japan KDD Research and Development Laboratories Inc. Japan IIT Delhi India Chilika Development Authority India WWF-India India System Giken corporation Japan PCCF Wildlife Orissa India

ISBN: (纸本)9780933957374

The authors have developed a passive acoustic observation system to monitor Irrawaddy dolphins (Orcaella brevirostris) in Chilika lagoon. The system is designed to monitor the detailed underwater behavior of dolphins using a Short Base Line (SBL) system all through the day and night. The underwater sounds are recorded at a sampling frequency of 500 kHz with 16 bits resolution. This system was deployed in Chilika lagoon from 29th January to 3rd February and on 18th February in 2007. Experiments were carried out all through the night. By replacing the batteries and hard disks, the observation system was made to keep running all the time. Consequently, the authors succeeded in obtaining click data from Irrawaddy dolphins for a continuous duration of about 21-hour consecutively for each trial and about 1 TB of acoustic data was obtained in total. The data contained many high frequency signals, which are considered to be the snapping noise made by shrimp, which are typically found in warm shallow water areas such as Chilika lagoon. A de-noise calculation is developed and applied to the obtained data. A clear picture of trajectories of dolphins in the turbid environment of the Chilika lagoon can be observed that has never before been seen. In this paper, detailed ideas and descriptions of the set up and deployment of the system are presented. Furthermore, the de-noise calculation and the observed dolphin trajectories will be discussed.

关键词： Dolphins Underwater acoustics Monitoring Frequency Underwater technology Sampling methods Batteries Hard disks Acoustic noise Working environment noise

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A signal control system by optical LAN and design simplification

A signal control system by optical LAN and design simplifica...

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IEEE International Conference on systems, Man and Cybernetics

作者： Jun Nishiyama Hiroyuki Sugahara Tetsuya Okada Takashi Kunifuji Yamato Fukuta Masayuki Matsumoto Development Center of JR East Group East Japan Railway Company Limited Saitama Japan Signalling and Telecommunications Technology Division Railway Technical Research Institute Tokyo Japan Signalling System Management Center Electrical and Signal Network System Department East Japan Railway Company Limited Tokyo Japan

To replace railway interlocking device, it is necessary to set up a large number of signal cables and confirm wiring connections. There are possibilities of wiring errors that may cause serious transport disorders. We have developed a railway signal control system by optical LAN for the purpose of reduction of signal cables and wiring works. Moreover, all signal devices operate independently, designers have to handle all devices one by one and pay great attention to avoid causing harmful influence each other. We suggest data-driven control logic to make it easy to replace interlocking device. This logic is rearranged according to the field device in order to simplify and decrease design duties of designers. In this paper, we introduce this system, and describe software configuration of the system.

关键词： Optical control Control systems Local area networks Optical design Signal design Wiring Rail transportation Cables Logic devices Logic design

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Capacitated Reliability for Ad-hoc Networks

Capacitated Reliability for Ad-hoc Networks

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Annual Symposium on Reliability and Maintainability (RAMS)

作者： Jason L. Cook Jose Emmanuel Ramirez-marquez Quality Engineering & System Assurance Directorate Picatinny Arsenal US Army-Armament Research Development Engineering Center NJ USA Department of Systems Engineering and Engineering Management Stevens Institute of Technology Hoboken NJ USA

Ad-hoc networking is used because of its malleable topology. The absence of infrastructure allows for the hasty deployment and redeployment of a network. No preparation of the coverage area is needed because things like transmission towers or communication wire lines are not necessary. It is this distinctive attribute of ad-hoc networking that does not conform to the base assumption on which all current network reliability methods are founded; that connectivity is known a priori. The proliferation of ad-hoc networking warrants new network reliability methods that may be applied to analyze them. This paper describes the unique characteristics of ad-hoc networks, presents current research on ad-hoc networks, and presents a new method for approximating the reliability of an ad-hoc network which is capacity constrained

关键词： Ad hoc networks Network topology Telecommunication network reliability Poles and towers IP networks Wire Costs Employment Switches Wiring

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The detailed Analysis of field emission under Stabilized Operation using field effect transistor

The detailed Analysis of field emission under Stabilized Ope...

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20th International Vacuum Nanoelectronics Conference (IVNC 2007)

作者： Yoichiro Neo Takahiro Matsumoto Hidetaka Shimawaki Hidenori Mimura Kuniyoshi Yokoo Research Institute of Electronics Shizuoka University Hamamatsu Japan Research and Development Center Stanley Electric Corporation Tsukuba Japan Department of System and Information Engineering Hachinohe Institute of Technology Hachinohe Japan Ideal Star Inc 6-6-3 Minamiyoshinari Aobaku Sendai 989-3204 Japan

Field emitters show step, spike and flicker noises in their emission currents, even they are operated in ultra high vacuum [1]. Besides, field emitter arrays [FEA] are strongly required to omit these noises and to control current fluctuation for the commercial product, such as a Flat panel display. The field emission current controlled by field effect transistor [FET] and thin film transistor [TFT] was already proposed [2, 3] and manufactured. In order to obtain enough current for phosphor irradiation, the FEA extraction gate voltage was applied of bias voltage up to about 100V. To enlarge the driving voltage range, multi-gate and light doped drain region were induced as the optimized structure. The several hundred square micrometers were occupied by TFT. As result, integration and downsizing pixel area for high vision television became difficult. We studied the detailed analysis on stability operation mechanism of field emission tip using outside connected FET and found another factor to control emission fluctuation.

关键词： FETs Thin film transistors Cathodes Anodes 1f noise Fluctuations Phosphors Voltage control Information analysis research and development

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A Demonstration Project in Hachinohe: Microgrid with Private Distribution Line

A Demonstration Project in Hachinohe: Microgrid with Private...

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IEEE International Conference on system of systems Engineering (SoSE)

作者： Yasuhiro Kojima Masanobu Koshio Shizuka Nakamura Hitoshi Maejima Yasushi Fujioka Tadahiro Goda Advanced Technology Research and Development Center Mitsubishi Electric Corporation Limited Amagasaki Hyogo Japan Kobe Works Mitsubishi Electric Corporation Limited Kobe Hyogo Japan Energy System Research Group Mitsubishi Research Institute Inc. Tokyo Japan Department of Electrical and Electronic Engineering Kyushu University Fukuoka Japan

Dispersed generators have been expected to provide effective measures for tackling issues such as energy cost reduction, environmental preservation, and or energy security. Against this backdrop, microgrids have attracted much attention in recent years, In this paper, first, the basic concept of a microgrid will be outlined. Next, the results from a field test of a "regional power grid" will be discussed. Emphasis is placed on the energy management system, which organizes controllable and uncontrollable dispersed generators into a single controlled unit while minimizing operational costs and environmental impacts. The system has been in operation since October 2005 and has proven a promising way to facilitate greater introduction of dispersed generators, especially photovoltaic and wind power generation systems.

关键词： Costs Control systems Distributed power generation Wind energy generation Dispersion Energy measurement Power system security Testing Power grids Energy management

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Walking Phase Recognition for People with Lower Limb Disability

Walking Phase Recognition for People with Lower Limb Disabil...

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IEEE International Conference on Rehabilitation Robotics (ICORR)

作者： Sang Wan Lee Taeyoub Yi Jeong-Su Han Hyoyoung Jang Heon-Hui Kim Jin-Woo Jung Zeungnam Bien Electrical Engineering and Computer Science Department Korean Advanced Institute of Science and Technology Daejeon South Korea Core Technology Laboratory Digital Appliances Research and Development Center Samsung Electronics Company Limited Suwon South Korea Human-friendly Welfare Robot System Engineering Research Center Korean Advanced Institute of Science and Technology Daejeon South Korea Computer Engineering Department Dongguk University Seoul South Korea

This paper presents a total solution on EMG signal-based walking phase recognition for people with lower limb disability. Various environmental factors such as sensed location, walking speed, and ground inclination are taken into consideration in all the phases of signal sensing, feature extraction, feature selection, and classification. Based on analysis on fourteen well-known feature extraction methods in varying environmental situation, this paper proposes a methodology for selecting a good feature set, and then demonstrates effectiveness of the proposed approach with the classification results.

关键词： Legged locomotion Electromyography Muscles Feature extraction Environmental factors Humans Rehabilitation robotics Robots systems engineering and theory Working environment noise

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Benchmarking the PSP Compact Model for MOS Transistors

Benchmarking the PSP Compact Model for MOS Transistors

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IEEE International Conference on Microelectronic Test Structures

作者： Xin Li Weimin Wu Amit Jha Gennady Gildenblat Ronald van Langevelde Geert D.J. Smit Andries J. Scholten Dirk B.M. Klaassen Colin C. McAndrew Josef Watts Michael Olsen Geoffrey Coram Samir Chaudhry James Victory Department of Electrical Engineering Arizona State University Tempe AZ USA Philips Research Laboratories Eindhoven Netherlands NXP Corporate Research Eindhoven Netherlands Freescale Semiconductor Inc. Tempe AZ USA TIBM Semiconductor Research and Development Center System and Technology Group Essex Junction VT USA IBM Semiconductor Research and Development Center Hopewell Junction NY USA Analog Devices Inc.orporated Wilmington MA USA Jazz Semiconductor Newport Beach CA USA

Recently, the PSP model was selected as the first surface-potential-based industry standard compact MOSFET model. This work presents the results of several qualitative "benchmark" tests that over the last two years were used to verify the physical behavior of the new model and its usefulness for future generations of CMOS IC design. These include newly developed tests and previously unavailable experimental data stemming from low-power, RF, mixed-signal, and analog applications of MOSFETs.

关键词： Circuit testing USA Councils Benchmark testing Integrated circuit modeling Semiconductor device modeling MOSFET circuits Radio frequency research and development Microelectronics Laboratories

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Effect of texture of AZ31 magnesium alloy sheet on mechanical properties and formability at high strain rate

Effect of texture of AZ31 magnesium alloy sheet on mechanica...

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作者： Kohzu, Masahide Hironaka, Tomoya Nakatsuka, Shota Saito, Naobumi Yoshida, Fusahito Naka, Tetsuo Okahara, Haruo Higashi, Kenji Department of Materials Science Graduate School of Engineering Osaka Prefecture University Sakai 599-8531 Japan Chubu Center National Institute of Advanced Industrial Science and Technology Nagoya 462-8510 Japan Department of Mechanical System Engineering Graduate School of Engineering Hiroshima University Higashihiroshima 739-8527 Japan Department of Maritime Technology Yuge National College of Maritime Technology Yuge 794-2593 Japan Corporate Planning Office Kasatani Co. Ltd. Osaka 532-0036 Japan Osaka Prefecture University Research and Development Lab. Daido Steel Co. Ltd. Nagoya 457-8545 Japan

The mechanical properties and formability of AZ31 magnesium alloy strips having different textures were investigated at a high strain rate based on that occuring in mass production by press forming. Forming at a high strain rate on the order of 100 s-1 requires a high temperature of over 473 K. To obtain accurate stress-strain curves, a high-speed testing machine that can maintain a constant true strain rate was used, and the change in gauge length on a test piece in a furnace was measured during the testing time of about 0.5 s. For the specimens, rolled strips consisting of fine grains (about 10 μm) and an extruded strip consisting of coarse grains (about 40 μm) were used. The {0001} textures of the extruded strip and one of the rolled strips were strongly oriented parallel to the rolled surface, but the texture of another rolling strip had two peaks that were inclined at 5-15 deg in front of and behind the rolling direction. At the high strain rate of 100 s-1, elongation decreased for every specimen. Nevertheless, a limiting drawing ratio (LDR) of 2.1-2.2 was obtained under uniform heating above 503 K in all the specimens except for the extruded strip. The high LDR of the rolled strip having a two-peak texture was maintained in forming at temperatures down to 473 K, in contrast to the LDR of the strongly oriented rolled strip, which reduced rapidly when formed at temperatures less than 503 K. © 2007 The Japan Society for technology of Plasticity.

关键词： Magnesium alloys

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Reliability aspects of gate oxide under ESD pulse stress

Reliability aspects of gate oxide under ESD pulse stress

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Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)

作者： Adrien Ille Wolfgang Stadler Thomas Pompl Harald Gossner Tilo Brodbeck Kai Esmark Philipp Riess David Alvarez Kiran Chatty Robert Gauthier Alain Bravaix Infineon Technologies Munich Germany Laboratoire Matériaux et Microélectronique de Provence (L2MP)-UMR CNRS 6137 Centre St Jérôme-Case 252 Université de Provence Toulon France IBM Semiconductor Research & Development Center System and Technology Group Essex Junction VT USA

Power law time-to-breakdown voltage acceleration is investigated down to ultra-thin oxides (1.1 nm) in the ESD regime in inversion and accumulation. Breakdown modes, oxide degradation and device drifts under ESD like stress are discussed as function of the oxide thickness. The consequent impacts on the ESD design window are presented.

关键词： Electrostatic discharge Stress Voltage Acceleration Degradation Electric breakdown CMOS technology Earth Observing system MOS devices Power system reliability

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