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Robust adaptive fuzzy control for a class of uncertain servomechanism systems

Robust adaptive fuzzy control for a class of uncertain servo...

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IEEE Region 10 International Conference TENCON

作者： U. Komin S. Phoojaruenchanachai S. Chatratana S. Kuntanapreeda National Electronics and Computer Technology Center Thailand Research and Development Center for Intelligent System King Mongkut''s Institute of Technology North Bangkok Thailand

In this paper an adaptive fuzzy control technique is presented for a class of uncertain mechanical systems. The uncertainties are mainly caused by mechanical friction and unbalanced load. The fuzzy logic system is employed to compensate the effect of the friction and the unbalanced load. The technique does not require a complete mathematical model or a priori knowledge about the system structure. By combining with a sliding mode control strategy, the adaptive fuzzy controller guarantees the stability of the closed loop system as well as the convergence of tracking errors. In this work we also constructed an actual mechanical plant to test the performance of the designed controller. Experimental results verify that the dynamic behaviors of the proposed control systems are robust with regarding to uncertainties and significantly improve tracking accuracy over a conventional adaptive PD controller.

关键词： Robust control Programmable control Adaptive control Fuzzy control Servomechanisms Sliding mode control Control systems Uncertainty Friction Mechanical systems

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A practical stereo scheme for obstacle detection in automotive use

A practical stereo scheme for obstacle detection in automoti...

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International Conference on Pattern Recognition

作者： H. Nakai N. Takeda H. Hattori Y. Okamoto K. Onoguchi Multimedia Laboratory Corporate Research & Development Center Toshiba Corporation Japan Broadband System LSI Development Center Semiconductor Company Toshiba Corporation Japan Department of Electrical and Information System Engineering Faculty of Science and Technology Hirosaki University Japan

We propose a novel stereo scheme for obstacle detection which is aimed at practical automotive use. The basic methodology involves simple region matching between images, observed from a stereo camera rig, where it is assumed the images are related by a pseudo-projective transform. It provides an effective solution for determining boundaries of obstacles in noisy conditions, e.g. caused by weather or poor illumination, which conventional planar projection approaches cannot cope with. The linearity of the camera model also contributes significantly to compensation of road inclination. Essentially, precise lane detection and prior knowledge concerning obstacles or ambient conditions are unnecessary and the proposed scheme is therefore applicable to a wide variety of outdoor scenes. We have also developed a multi-VLIW processor that fulfills the essential specifications for automotive use. Our scheme for obstacle detection is largely reflected in the processor design so that real-time on-board processing can be realized with acceptable cost to both automobile users and manufacturers. The implementation of a prototype and experimental results illustrates our method.

关键词： Automotive engineering Cameras Lighting Linearity Roads Layout Process design Costs Automobiles Manufacturing processes

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A simulation-based control system - A case study for distillation columns

A simulation-based control system - A case study for distill...

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2004 IEEE International Conference on Control Applications

作者： Yumoto, Takamasa Ohmori, Hiromitsu Ohtani, Tetsuya Engineering and Development Div. Omega Simulation Co. Ltd. 2-20-9 Nishi-Waseda Shinjyuku-ku Tokyo Japan Faculty of Science and Technology Dept. of System Design Engineering Keio University 3-14-1 Hiyoshi Kohoku-ku Yokohama Kanagawa Japan Instrum. and Control Research Center Yokogawa Electric Corporation 2-9-32 Nakacho Musashino-shi Tokyo Japan

In this paper we provide a novel simulation-based control system for the purpose of minimizing an objective function, followed by similar research areas such as dynamic optimization and model predictive control. Our target processes have large nonlinearity, multi manipulated variables and multi control variables. Then the control system scheme and an optimization algorithm are provided. We also illustrate the results obtained from application of a depropanizer distillation column using a rigorous plant-wide dynamic simulator. In addition, our future controller design trend intended to attenuate the effect of disturbances are outlined in the final section. ©2004 IEEE.

关键词： Control system analysis

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Summary of the 2004 CFD validation workshop on Synthetic Jets And Turbulent Separation Control

Summary of the 2004 CFD validation workshop on Synthetic Jet...

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2nd AIAA Flow Control Conference 2004

作者： Rumsey, C.L. Gatski, T.B. Sellers, W.L. Vatsa, V.N. Viken, S.A. NASA Langley Research Center Hampton VA 23681-2199 United States Computational Modeling and Simulation Branch Mail Stop 128 United States Flow Physics and Control Branch Mail Stop 170 United States Systems Technology Development ASPO Small Aircraft Transportation Systems Mail Stop 916 United States

ISBN: (纸本)9781624100307

A CFD validation workshop for synthetic jets and turbulent separation control (CFDVAL2004) was held in Williamsburg, Virginia in March 2004. Three cases were investigated: synthetic jet into quiescent air, synthetic jet into a turbulent boundary layer crossflow, and flow over a hump model with no-flow-control, steady suction, and oscillatory control. This paper is a summary of the CFD results from the workshop. Although some detailed results are shown, mostly a broad viewpoint is taken, and the CFD state-of-the-art for predicting these types of flows is evaluated from a general point of view. Overall, for synthetic jets, CFD can only qualitatively predict the flow physics, but there is some uncertainty regarding how to best model the unsteady boundary conditions from the experiment consistently. As a result, there is wide variation among CFD results. For the hump flow, CFD as a whole is capable of predicting many of the particulars of this flow provided that tunnel blockage is accounted for, but the length of the separated region compared to experimental results is consistently overpredicted. © 2004 by the American Institute of Aeronautics and Astronautics, Inc.

关键词： Computational fluid dynamics

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Ultra wide bandwidth performance of high-density wiring interposer for 3D packaging

Ultra wide bandwidth performance of high-density wiring inte...

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Electronic Components and technology Conference (ECTC)

作者： K. Kikuchi S. Segawa Eun-Sil Jung Y. Nemoto M. Umemoto H. Nakagawa K. Tokoro M. Aoyagi National Institute for Advanced Industrial Science and Technology Tsukuba Ibaraki Japan PI Research and Development Company Limited Yokohama Kanagawa Japan Tsukuba Research Center Electronic System Integration Technology Research Development Association of Super-Advanced Electronics Technologies (ASET) Tsukuba Center Inc. Tsukuba Ibaraki Japan

We have demonstrated a high-density wiring interposer for 10 GHz 3D packaging using a photosensitive multiblock copolymerized polyimide. This new polyimide can realize micron-sized fine patterns without the pattern shrinkage because of not requiring high-temperature thermal curing. The polyimide has good electric properties such as high breakdown voltage and low dielectric constant. Therefore, it is considered that by introducing this photosensitive polyimide as an insulator of the interposer, a high-performance interposer for LSI packaging can be realized. We confirmed experimentally that the high-density wiring interposer could be fabricated using the polyimide and the gold metal. From time domain reflectometry (TDR) measurement by using a specially prepared 20-/spl mu/m-pitch microwave contact probe, it was found that the characteristic impedance of the stripline is within 55.2 /spl Omega//spl plusmn/11.5 % at the central 10-mm-square area of the interposer.

关键词： Bandwidth Wiring Packaging Polyimides Curing Dielectric constant Dielectrics and electrical insulation Large scale integration Gold Reflectometry

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An adaptive security/performance encryption system

An adaptive security/performance encryption system

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International Conference on Electrical, Electronic and Computer Engineering (ICEEC)

作者： M.E. El-Hennawy Y.H. Dakroury M.M. Kouta M.M. El-Gendy Computer and System Engineering Department Ain Shams University Cairo Egypt Arab Academy for Science Technology and Maritime Transport Cairo Egypt Research Development Center Cairo Egypt

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Challenge of low-k materials for 130, 90, 65 nm node interconnect technology and beyond

Challenge of low-k materials for 130, 90, 65 nm node interco...

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International Electron Devices Meeting (IEDM)

作者： H. Miyajima K. Watanabe K. Fujita S. Ito K. Tabuchi T. Shimayama K. Akiyama T. Hachiya K. Higashi N. Nakamura A. Kajita N. Matsunaga Y. Enomoto R. Kanamura M. Inohara K. Honda H. Kamijo R. Nakata H. Yano N. Hayasaka T. Hasegawa S. Kadomura H. Shibata T. Yoda Process and Manufacturing Engineering Center Semiconductor Company Toshiba Corporation Japan Semiconductor Technology Development Division Semiconductor Solutions Network Company Sony Corporation Yokohama Japan SoC Research and Development Center Semiconductor Company Toshiba Corporation Japan SoC Research and Development Center Semiconductor Company Toshiba Corporation System LSI Division I Semiconductor Company Japan System LSI Division I Semiconductor Company Toshiba Corporation System LSI Division I Semiconductor Company Toshiba Corporation Japan

In order to realize highly reliable low-k/Cu interconnects, optimum BEOL structures were developed for 130, 90 and 65 node logic devices respectively. For 65 nm node BEOL structure, the conventional monolithic dual damascene (DD) structure was replaced by the hybrid-DD structure with PAr/SiOC stack films. It shows high extendibility to the next generation using newly developed technologies, such as eBeam cure and damage restoration techniques.

关键词： Dielectric materials Logic devices Plasma applications Resists Materials reliability Process design Design optimization Adhesives Plasma properties Plasma materials processing

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Impact of parasitic resistance and silicon layer thickness scaling for strained-silicon MOSFETs on relaxed Si/sub 1-x/Ge/sub x/ virtual substrate

Impact of parasitic resistance and silicon layer thickness s...

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International Electron Devices Meeting (IEDM)

作者： H. Kawasaki K. Ohuchi A. Oishi O. Fujii H. Tsujii T. Ishida K. Kasai Y. Okayama K. Kojima K. Adachi N. Aoki T. Kanemura D. Hagishima M. Fujiwara S. Inaba K. Ishimaru N. Nagashima H. Ishiuchi Toshiba Corporation Semiconductor Company Yokohama Japan System LSI Division I SoC Research and Development Center Yokohama Japan Advanced LSI Technology Laboratory Toshiba Corporation Yokohama Japan Semiconductor Technology Development Group Sony Corporation Yokohama Japan

This paper discusses the root causes of the fact that only slight performance improvement of MOSFET with strained-Si substrate has been achieved in short channel region (L < 100 nm). The performance improvement in short channel region is found to deteriorate mainly due to the parasitic resistance increase and tensile stress relaxation in the strained-Si layer. In regard to the parasitic resistance and the stress relaxation in small device geometry, the scaling impacts of strained-Si layer thickness (T/sub ss/) are investigated from the viewpoint of both DC and AC characteristics. Within this work, T/sub ss/ reduction down to 5 nm improves the current drive (I/sub d/) of nFET up to 6 % (L < 50 nm) compared with conventional bulk nFET. Propagation delay time (/spl tau//sub pd/) improvement in CMOS inverter is also observed to be more than 15 %. Finally, the impurity profile optimization is proposed to improve MOSFET performance toward the 45 nm node CMOS era.

关键词： MOSFETs Impurities Silicon germanium Germanium silicon alloys Degradation Large scale integration Tensile stress Dielectric substrates Electronic mail Propagation delay

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Bidding market based on single price model with network constraints

Bidding market based on single price model with network cons...

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IEEE PES Power systems Conference and Exposition, PSCE

作者： S. Fukutome T. Wachi L. Chen Y. Makino G. Koshimizu System Engineering Department JP Business Service Corporation Koto Tokyo Japan Department of Electrical Engineering and Electronics Osaka Sangyo University Daito Osaka Japan IT & Power System Engineering Laboratory Technology Development Center Electric Power Development Co. Limited Chigasaki Research Institute Chigasaki Kanagawa Japan

This paper aims to develop a single price auction model with AC transmission network for Electricity Market in Japan, based on the principle of maximizing social surplus. Specifically, we first formulate the auction market as a nonlinear optimisation problem, which has almost the same form as the conventional optimal power flow problem, and then propose an algorithm to derive both market clearing price and trade volumes of participants even for the case of market-splitting. As indicated in the paper, the proposed approach can be used not only for the price evaluation of auction or bidding market but also for analysis of bidding strategy and congestion management. Several numerical examples are used to demonstrate effectiveness of our method.

关键词： Electricity supply industry ISO Power engineering and energy Load flow Electricity supply industry deregulation systems engineering and theory Voltage Europe Costs Power markets

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Integration of interconnect process highly manufacturable for 65nm CMOS platform technology (CMOS5)

Integration of interconnect process highly manufacturable fo...

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Symposium on VLSI technology

作者： K. Honda M. Kanda R. Ishizuka Y. Moriuchi Y. Matsubara M. Habu T. Yoshida S. Matsuda H. Kittaka H. Miyajima T. Hachiya A. Kajita T. Usui N. Nagashima R. Kanamura Y. Okamoto S. Yamada T. Noguchi System LSI Division Semiconductor Company Toshiba Corporation Japan Process & Manufacturing Engineering Center Semiconductor Company Toshiba Corporation Japan SoC Research & Development Center Semiconductor Company Toshiba Corporation Japan Semiconductor Technology Development Division Semiconductor Solutions Network Company Sony Corporation Yokohama Japan

ISBN: (纸本)0780382897

PAE/SiOC/SiC hybrid dual damascene process with low-k (k=2.5) dielectric layer for 65nm-node was successfully integrated. The EB curing technique of the low-k dielectric was selected to maintain enough adhesion strength. Package feasibility test was performed successfully. To evaluate the impact of the ILD process on the device performance, gate oxide characteristics was carefully studied and no degradation was observed. Functional logic and memory blocks were fabricated using multi level interconnections. High manufacturability of the hybrid DD interconnects process for the 65nm CMOS platform is demonstrated.

关键词： CMOS technology Manufacturing processes CMOS process Dielectrics Silicon carbide Curing Adhesives Packaging Testing Performance evaluation

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