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systematic studies on fractal scan model for Flat Panel Display (FPD) controllers

International Journal of Manufacturing research 2011年第4期6卷 367-379页

作者： Xu, M. Ran, F. Chen, Z. School of Mechatronical Engineering and Automation Shanghai University Shanghai 200072 China Key Laboratory of Advanced Display and System Application Ministry of Education Shanghai University Shanghai 200072 China Microelectronic Research and Development Centre Shanghai University Shanghai 200072 China

This paper presents the design and logic implementation of the fractal scan algorithm based on the mathematical model of the optimal scan architecture. Through the exploration of the sub-space code sequences and bit code sequences for different grey levels, we deduce the general formulae for the sequences and propose the corresponding logic implementations including the fractal scanning IP core and the general grey-level controller for Flat Panel Display (FPD). The parameterised IP core for various grey levels, embedded in FPD scan controller, can efficiently increase the scan utilisation and imaging quality. This research provides a new engineering way to solve a pressing problem of high resolution FPD technology. Copyright © 2011 Inderscience Enterprises Ltd.

关键词： Controllers

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Preparation of photocrosslinkable polystyrene methylene cinnamate nanofibers via electrospinning

Preparation of photocrosslinkable polystyrene methylene cinn...

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作者： Yi, Chuan Nirmala, R. Navamathavan, R. Li, Xiang-Dan Kim, Hak-Yong Hubei Provincial Research Institute of Environmental Science Wuhan 430072 China Department of Bio-nano System Engineering Chonbuk National University Jeonju 561-756 Korea Republic of School of Advanced Materials Engineering Chonbuk National University Jeonju 561 756 Korea Republic of Hubei Key Laboratory for Catalysis and Materials Science College of Chemistry and Materials Science South-Central University for Nationalities Wuhan 430074 China Center for Healthcare Technology and Development Chonbuk National University Jeonju 561 756 Korea Republic of

Nanoscaled photocrosslinkable polystyrene methylene cinnamate (PSMC) nanofibers were fabricated by electrospinning. The PSMC was prepared by the modification of polystyrene as a starting material via a two-step reaction process, chloromethylation and esterification. The chemical structure of PSMC was confirmed by 1H NMR and Fourier transform infrared spectroscopy (FT-IR). The photosensitivity of the PSMC was investigated using ultraviolet (UV) spectroscopic methods. Electrospun PSMC nanofiber mat showed excellent solubility in many organic solvents. UV irradiation of the electrospun mats led to photodimerization to resist dissolving in organic solvents. The morphology of the nanofiber was observed by scanning electron microscopy (SEM) and the result indicated that the average diameter of nanofibers is 350 nm and the crosslinked nanofibers were not collapsed after dipping into organic solvent showing good solvent-stability. This photocrosslinked nanofibers has the potential application in filtration, catalyst carrier and protective coating. Copyright © 2011 American Scientific Publishers. All rights reserved.

关键词： Nanofibers

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Green Aviation Papers, Call and Recognition

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JOURNAL OF AIRCRAFT 2011年第1期48卷 1-1页

作者： Weeks, Thomas M. AIAA United States Department of Aerospace Engineering Alfred Gessow Rotorcraft Center University of Maryland United States RED Associates Denmark University of Dayton United States U.S. Air Force Research Laboratory Wright-Patterson Air Force Base United States Boeing Company Norway Department of mechanical and aeronautical engineering University of California Davis United States Boeing Commercial Airplanes Norway *** United States Department of Aerospace Engineering Texas AandM University United States Department of Engineering Design and Innovation Natural Sciences and Engineering Research Council University of Western Ontario Canada NASA Ames Research Center United States Advanced Joint Air Combat System (AJACS) Speed-Agile Configuration Development (SACD) United States

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Performance Analysis of 3D-IC for Multi-Core Processors in sub-65nm CMOS technologies

Performance Analysis of 3D-IC for Multi-Core Processors in s...

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International Symposium on Circuits and systems Nano-Bio Circuit Fabrics and systems (ISCAS 2010)

作者： Nomura, Kumiko Abe, Keiko Fujita, Shinobu Kurosawa, Yasuhiko Kageshima, Atsushi Advanced LSI Technology Laboratory Corporate R and D Center Toshiba Corporation Japan Center of Semiconductor Research and Development Toshiba Semiconductor Company Japan System LSI Division Toshiba Semiconductor Company Japan

ISBN: (纸本)9781424453092

Three-dimensional integrated circuits (3D-IC) have the potential to reduce interconnect length and improve performance especially in sub-65nm CMOS technologies. This paper describes design and performance analysis of the 3D-IC in sub-65nm CMOS technologies based on the accurate calculation of interconnects delays using 16-core processors as case studies. Performance improvement of the 3D-IC vs. 2D-IC is increased as CMOS scales down, which is consistent with the expected trend. The performance improvement is over 20%. Furthermore, performance of the 3D-IC in 65 nm (or 45 nm) CMOS technology is superior to that of the 2D-IC in 45 nm (or 32 nm) CMOS technology. It indicates that design conversion from 2D-IC to 3D-IC is superior to the CMOS technology migration according to COMS scaling. Reduction in repeater buffers and area overhead is also estimated.

关键词： CMOS integrated circuits

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High-resolution and site-specific SSRM on S/D engineering

High-resolution and site-specific SSRM on S/D engineering

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10th International Workshop on Junction Technology, IWJT-2010

作者： Zhang, L. Saitoh, M. Koike, M. Takeno, S. Tanimoto, H. Adachi, K. Yasutake, N. Kusunoki, N. Advanced LSI Technology Laboratory Corporate Research and Development Center Toshiba Corporation Japan Center for Semiconductor Research and Development Japan System LSI Division Semiconductor Company 1 Komukai-Toshiba-Cho Saiwai-Ku Kawasaki 212-8582 Japan

ISBN: (纸本)9781424458691

Recently, we reported significantly improved spatial resolution in scanning spreading resistance microscopy (SSRM) by measuring in a vacuum. In this work, we demonstrate the 1-nm-spatial resolution of SSRM on pn junction delineation by comparing with three-dimensional device simulation. A five-order dynamic range of carrier concentration is also confirmed on staircase sample. A systematic comparison between pFETs/nFETs on (110) and (100) substrates has been carried out with SSRM. The S/D of (110) pFETs shows less lateral distribution than that of (100), strongly indicating 2D-channeling effect of boron ion implantation. We also succeeded in a new sample-making method by fully FIB pick up, enabling site-specific SSRM characteristics for failure analysis and for further scaled devices. © 2010 IEEE.

关键词： Carrier concentration

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VLSI implementation of sub-pixel interpolator for AVS encoder

VLSI implementation of sub-pixel interpolator for AVS encode...

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2010 International Conference on Life system Modeling and Simulation, LSMS 2010 and the 2010 International Conference on Intelligent Computing for Sustainable Energy and Environment, ICSEE 2010

作者： Guanghua, Chen Anqi, Wang Dengji, Hu Shiwei, Ma Weimin, Zeng School of Mechatronics Engineering and Automation Shanghai Key Laboratory of Power Station Automation Technology Shanghai University Shanghai 200072 China Key Laboratory of Advanced Display and System Applications Microelectronic Research and Development Center Shanghai University Shanghai 200072 China

Interpolation is the main bottleneck in AVS real-time high definition video encoder for its high memory bandwidth and large calculation complexity caused by the new coding features of variable block size and 4-tap filter. In this paper, a high performance VLSI architecture of interpolation supporting AVS Baseline@L4 is presented. Vertical redundant data reuse, horizontal redundant data reuse and sub-pixel data reuse schemes are presented to reduce memory bandwidth and processing cycle. The separated 1-D interpolation filters are used to improve throughput and hardware utilization. The proposed design is implemented on FPGA with operating frequency of 150MHz and can support 1080p (1920x1080)/30fps AVS real-time encoder. It is a useful intellectual property design for real-time high definition video application. © 2010 Springer-Verlag.

关键词： Pixels

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Improved Delay Fault Coverage in SoC Using Controllable Multi-Scan-Enable

Improved Delay Fault Coverage in SoC Using Controllable Mult...

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2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

作者： Jin-yi ZHANG Xu-hui HUANG Wan-lin CAI Han-yi WENG Key Laboratory of Advanced Displays and system Application Ministry of Education Shanghai Universi Microelectronic Research & Development Center Shanghai University Key aboratory of Advanced Displays and system Application Ministry of Education Shanghai Universit

ISBN: (纸本)9781424457977

This paper presents a method of multi-Scan-Enable DFT design for at-speed scan testing to improve transition fault coverage. Base on the method, we build a novel TR-TC (Test Resources-Test Coverage) associated test cost mathematical model to effectively control the complexity of at-speed DFT design and establish the optimization number of ScanEnable, which provides a reliable target control value in multi-Scan-Enable DFT design for at-speed scan testing. Experiment results for transition fault coverage improvement on three industrial SoC circuits and the upper limit of the number of Scan-Enable are presented.

关键词： sweep test scanning fault latency controlling value fault coverage discrete Fourier transform Coverage test coverage Mathematical Model

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Performance analysis of 3D-IC for multi-core processors in sub-65nm CMOS technologies

Performance analysis of 3D-IC for multi-core processors in s...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Kumiko Nomura Keiko Abe Shinobu Fujita Yasuhiko Kurosawa Atsushi Kageshima Advanced LSI Technology Laboratory Corporate Research and Development Center Toshiba Corporation Japan Center of Semiconductor Research and Development Japan System LSI Division Toshiba Semiconductor Company Limited Japan

关键词： CMOS technology Performance analysis Three-dimensional integrated circuits Multicore processing CMOS process Integrated circuit interconnections Delay Integrated circuit technology Through-silicon vias Large scale integration

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Improved delay fault coverage in soc using controllable multi-scan-enable

Improved delay fault coverage in soc using controllable mult...

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2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology

作者： Zhang, Jin-Yi Huang, Xu-Hui Cai, Wan-Lin Weng, Han-Yi Key Laboratory of Advanced Displays and System Application Ministry of Education Shanghai University No.149 Yanchang Road Shanghai 200072 China Microelectronic Research and Development Center Shanghai University No.149 Yanchang Road Shanghai 200072 China Ministry of Education No.149 Yanchang Road Shanghai 200072 China

ISBN: (纸本)9781424457984

This paper presents a method of multi-Scan-Enable DFT design for at-speed scan testing to improve transition fault coverage. Base on the method, we build a novel TR-TC (Test Resources-Test Coverage) associated test cost mathematical model to effectively control the complexity of at-speed DFT design and establish the optimization number of Scan-Enable, which provides a reliable target control value in multi-Scan-Enable DFT design for at-speed scan testing. Experiment results for transition fault coverage improvement on three industrial SoC circuits and the upper limit of the number of Scan-Enable are presented. ©2010 IEEE.

关键词： Design for testability

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The implementation of the global scheduling strategy

The implementation of the global scheduling strategy

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2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology

作者： Zhang, Jinyi Cai, Wanlin Wang, Chunhua Key Laboratory of Advanced Displays and System Application Ministry of Education Shanghai University No.149 Yanchang Road Shanghai 200072 China Microelectronic Research and Development Center Shanghai University No.149 Yanchang Road Shanghai 200072 China Ministry of Education No.149 Yanchang Road Shanghai 200072 China

ISBN: (纸本)9781424457984

Today the research on design for testability is becoming the research priority in the filed of SoC. However, the traditional research is limited in top level of SoC and it ignores the inference resulting from the scheduling strategy in IP-core level. In addition, the work on stage of SoC overly focuses on researching the minimum testing time of different WSC. It ignores the relationship between the WSC and testing time. So the traditional research doesn't play a significant role in design of SoC. In order to achieve the full use of testing resources, a bottom-up global scheduling strategy based on WSC balancing scan chain is proposed in this paper. In this paper, we verify the algorithm and reusability of this strategy upon the ITC'02 benchmark. ©2010 IEEE.

关键词： Chains

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