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检索条件"机构=Research and Development of Advanced Software System Laboratory"

共 346 条记录，以下是241-250 订阅

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pService: Towards Similarity Search on Peer-to-Peer Web Services Discovery

pService: Towards Similarity Search on Peer-to-Peer Web Serv...

引用

International Conference on Advances in P2P systems (AP2PS)

作者： Gang Zhou Jianjun Yu National Digital Switching System Engineering and Technological Research and Development Center China State Key Laboratory of Software Development Environment Beihang University China Computer Network Information Center Chinese Academy and Sciences China

We present the design of pService system for P2P Web services discovery supporting similarity search with its locality-preserving feature based on modified Skip Graph. In pService, the most important property (e.g. service name) of a service is viewed as the indexing key of a peer node. The other properties are extracted as multiattributes which would be mapped into one-dimensional indices using HSFC (Hilbert Space Filling Curve), and assigned to membership vector of the peer node. These two features help to support similarity search in two aspects: peer nodes with similar indexing keys would be distributed neighborly, peer nodes with similar indices will connect to each other through routing table. Our evaluation showed that the pService performs considerable Web services discovery efficiency.

关键词： Peer to peer computing Web services Indexing Routing Hilbert space Filling Search engines Data structures Switching systems Design engineering

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Test scheduling of SOC IP interconnect for static and SI faults

Test scheduling of SOC IP interconnect for static and SI fau...

引用

Institution of Engineering and Technology International Communication Conference on Wireless Mobile and Computing

作者： Jinyi, Zhang Xiaodong, Yang Dong, Zhang Yi, Yang Key Laboratory of Special Fiber Optics and Optical Access Networks Ministry of Education Shanghai University No. 149 Yanchang Road Shanghai 200072 China Microelectronic Research and Development Center Shanghai University No. 149 Yanchang Road Shanghai 200072 China Key Laboratory of Advanced Displays and system Application Ministry of Education Shanghai University No. 149 Yanchang Road Shanghai 200072 China

ISBN: (纸本)9781849191388

This paper proposes a scheduling method of SOC (system on Chip) interconnect test complied with IEEE Std 1500 based on Genetic Algorithm. The algorithm figures out optimal scheduling of interconnect test for high utility of TAM (Test Access Mechanism) width, and eight fixed test patterns are used to cover static and Signal Integrity faults based on MA (Maximum Aggressor faults model) for specific victim. Experiment is implemented in ITC'02 benchmark to prove the effectiveness of the algorithm solved with MATLAB toolbox.

关键词： Genetic algorithms

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Scheduling of balancing WSC for minimum IP testing time

Scheduling of balancing WSC for minimum IP testing time

引用

Institution of Engineering and Technology International Communication Conference on Wireless Mobile and Computing

作者： Zhang, Jinyi Cai, Wanlin Li, Jiao Huang, Xuhui Weng, Hanyi Key Laboratory of Special Fiber Optics and Optical Access Networks Ministry of Education Shanghai University No. 149 Yanchang Road Shanghai 200072 China Microelectronic Research and Development Center Shanghai University No. 149 Yanchang Road Shanghai 200072 China Key Laboratory of Advanced Displays and system Application Ministry of Education Shanghai University No. 149 Yanchang Road Shanghai 200072 China

ISBN: (纸本)9781849191388

Today the research on designing for testability is becoming very important in the filed of SoC. However, the traditional research is limited in top level of SoC. It does not really guarantee to improve the utilization of test resource of SoC and reduce the test time effectively in theory. This paper proposes that the focus of study will be extended to the IP core level. We can reduce the percentage of idle test time and achieve the minimum of test time in various IP cores through the establishment of scheduling strategy of balancing WSC (Wrapper Scan Chain) and the exchange ISC (Inter Scan Chain) heuristic algorithm. In this paper, we verify the scheduling strategy of balancing WSC in algorithm and reusability upon the ITC'02 benchmarks. The results show that the vast majority of percentage of idle test time is much less than 1% in the relationship set between the number m of balanced WSC and the test time TIP within each IP core. The results also can verify the importance of the research programme which is implemented in IP core level for improving the utilization of test resource and reducing the test time effectively in SOC.

关键词： Scheduling

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Network traffic simulation based on Network Processor

Network traffic simulation based on Network Processor

引用

International Conference on advanced Technologies for Communications, ATC

作者： Shuai Yuan Gang Zhou Baochao Tian Yi Jin State Key Laboratory of Software Development Environment Beihang University Beijing China National Digital Switching System Engineering & Technological Research Center Information Engineering University Zhengzhou China

Achievements of network traffic simulation provide realistic, feasible and accurate methods of measuring bandwidth, latency, jitter and so on. However as the development of networking technology, traditional manners are becoming insufficient to provide high bandwidth matching the real network, nor accurate statistics characteristic such as self-similarity. In this paper we propose the Network Traffic Simulation platform based on Network Processor (NTS-NP). The platform has achieved: 1) high bandwidth and real-time traffic generation; 2) high precision of self-similarity of the flow, which is now considered to be one of the basic characteristics of network traffic. In our platform, Cavium OCTEON CN3860 is chosen as the core in order to gain the ability of high speed packets assembling and transmitting, and direct control of the interface hardware. ON/OFF aggregation model is implemented to generate self-similarity and a discrete-event driven based algorithm is proposed to improve the traditional implementation of the model. We estimate the Hurst parameter of synthetic traffic by R/S statistics method and wavelet estimator. The validation of the platform is also empirically discussed and proved.

关键词： Telecommunication traffic Traffic control Bandwidth Statistics Communication system traffic control Delay Jitter Character generation Assembly Hardware

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High Bandwidth Real-Time Network Traffic Generation with Self-Similarity

High Bandwidth Real-Time Network Traffic Generation with Sel...

引用

International Conference on Computational Intelligence and software Engineering (CiSE)

作者： Shuai Yuan Gang Zhou Yi Jin State Key Laboratory of Software Development Environment Beihang University Beijing China National Digital Switching System Engineering & Technological Research Center Information and Engineering University Zhengzhou China

Network traffic generation has always been a hot spot in network measurement and simulation research. However, traditional methods of generating network traffic are either insufficient in fulfilling bandwidth requirement or matching the characteristics of a real network. In this paper we propose a platform of generating high bandwidth real-time network traffic with self-similarity characteristic. The high bandwidth real-time generating feature guarantees the feasibility and self-similarity characteristic makes the platform more reliable. In the platform, we choose Cavium OCTEON CN3860 as the core and implemented ON/OFF aggregation model in a discrete-event way. The Hurst parameter of synthetic traffic is estimated both by R/S statistics method and wavelet estimator. Although there are differences between two estimators in various kinds of conditions, the validation of the platform is empirically discussed and proved.

关键词： Bandwidth Telecommunication traffic Traffic control Computational modeling Character generation Computer networks Delay Circuit simulation Application specific integrated circuits Hardware

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Comparing Three Algorithms of Implementing ON/OFF Aggregation Model

Comparing Three Algorithms of Implementing ON/OFF Aggregatio...

引用

International Conference on Computational Intelligence and software Engineering (CiSE)

ON/OFF aggregation model is one of the efficient and accurate models for self-similar network traffic generation. In this paper we propose and compare three algorithms of implementing ON/OFF aggregation model, based on Cavium OCTEON CN3860 network processor, aimed to achieve high-bandwidth and real-time network traffic generation. The model is implemented in a multi-thread approach, in a token-bucket approach and in a discrete-event approach. The Hurst parameter of synthetic traffic is estimated by wavelet estimator, and the validation of the last algorithm is empirically discussed and proved.

关键词： Traffic control Telecommunication traffic Computational modeling Bandwidth Computer networks Delay Hardware Application specific integrated circuits software algorithms Programming

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The research of an Approach to Design Local Area Network Topology Based on Genetic Algorithm

The Research of an Approach to Design Local Area Network Top...

引用

International Symposium on Computational Intelligence and Design, ISCID

作者： Fei Teng Gang Zhou State Key Laboratory of Software Develop Environment Beijing Aeronautics and Astronautics University Beijing China National Digital Switching System Engineering and Technological Research and Development Center Zhengzhou Henan China

The topological design of local area network is a process to find the network with the best performance, minimum cost and highest reliability, under the objective and engineering constraints. The problem could be considered as a multi-objective optimization problem, owing to that it requires all kinds of network performances be optimized at the same time and keeps the cost minimum, and has been proven to be a NP-hard problem by some researchers. There is no existing effective determinant algorithm that can solve it so far. In this paper, we introduce the Pareto optimization theory, Pareto ranking technique and the Pareto converging genetic algorithm based on them, and a PCGA based algorithm for solving bicriteria network topology design problems of local area network, is presented, considering the network average delay and network cost. We also adopt the Pru¿fer number to represent chromosomes in order to ensure the tree topology of LAN. Besides, traditional crossover approach is improved to speed up the algorithm and a new variant based halting criteria is proposed to enhance the stability of the GA results. Thought the comparison between our results and that of exhausted search, our algorithm turns out to be correct and effective, and compared with the classic NPGA, the proposed method can search faster and produce topologies closer to the real Pareto-front.

关键词： Algorithm design and analysis Local area networks Network topology Genetic algorithms Cost function Reliability engineering Design engineering NP-hard problem Pareto optimization Biological cells

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Insight into the S/D engineering by high-resolution imaging and precise probing of 2D-carrier profiles with scanning spreading resistance microscopy

Insight into the S/D engineering by high-resolution imaging ...

引用

International Electron Devices Meeting (IEDM)

作者： Li Zhang Masumi Saitoh Atsuhiro Kinoshita Nobuaki Yasutake Akira Hokazono Nobutoshi Aoki Naoki Kusunoki Ichiro Mizushima Mitsuo Koike Shiro Takeno Junji Koga Advanced LSI Technology Laboratory Corporate Research & Development Center Toshiba Corporation Kawasaki Japan Center of Semiconductor Research and Development Toshiba Corporation Kawasaki Japan System LSI Division Toshiba Corporation Kawasaki Japan Process & Manufacturing Engineering Center Semiconductor Company Toshiba Corporation Kawasaki Japan

ISBN: (纸本)9781424456390

For the first time, high-resolution carrier imaging has been carried out on (110)/(100) pFETs and nFETs with scanning spreading resistance microscopy (SSRM). The S/D of (110) pFETs shows less lateral distribution than that of (100), strongly indicating 2D-channeling effect of boron I/I. Direct evidence has been shown that As out-diffusion under NiSi made conductive paths that degrade junction leakage on (110) nFETs. The Si:C influences on S/D profiles are also directly observed. We also succeeded in a full-FIB sample-making for the first time, showing the high potential of SSRM technology for further scaled devices.

关键词： High-resolution imaging Microscopy Degradation CMOSFETs Large scale integration Boron Electrical resistance measurement Circuits Bonding Laboratories

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Scheduling of balancing WSC for minimum IP testing time

Scheduling of balancing WSC for minimum IP testing time

引用

IET International Communication Conference on Wireless Mobile and Computing (CCWMC 2009)

作者： Jinyi Zhang Wanlin Cai Jiao Li Xuhui Huang Hanyi Weng Key Laboratory of Advanced Displays and system Application Ministry of Education Shanghai University Shanghai China Microelectronic Research & Development Center Shanghai University Shanghai China Key Laboratory of Special Fiber Optics and Optical Access Networks (Shanghai University) Ministry of Education

Today the research on designing for testability is becoming very important in the filed of SoC. However, the traditional research is limited in top level of SoC. It does not really guarantee to improve the utilization of test resource of SoC and reduce the test time effectively in theory. This paper proposes that the focus of study will be extended to the IP core level. We can reduce the percentage of idle test time and achieve the minimum of test time in various IP cores through the establishment of scheduling strategy of balancing WSC (Wrapper Scan Chain) and the exchange ISC (Inter Scan Chain) heuristic algorithm. In this paper, we verify the scheduling strategy of balancing WSC in algorithm and reusability upon the ITC'02 benchmarks. The results show that the vast majority of percentage of idle test time is much less than 1% in the relationship set between the number m of balanced WSC and the test time T IP within each IP core. The results also can verify the importance of the research programme which is implemented in IP core level for improving the utilization of test resource and reducing the test time effectively in SOC.

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A scan chains combined-balance strategy for hierarchical SoC DFT

A scan chains combined-balance strategy for hierarchical SoC...

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International Conference on ASIC

作者： Jinyi Zhang Dong Zhang Xiaodong Yang Yi Yang Key Laboratory of Advanced Displays and system Application and Key Laboratory of Special Fiber Optics and Optical Access Networks Ministry of Education Shanghai University China School of Communication and Information Engineering Shanghai University China Microelectronic Research & Development Centre Shanghai University China

Intellectual property (IP) cores reused technology improves system-on-a-chip (SoC) design productivity. However, with more IP cores embedded in the deeper levels, the hierarchical architecture of SoC becomes complex, which also makes the test difficult. A scan chains combined-balance (SCCB) strategy is proposed in this paper to reconfigure and balance the scan chains, which helps reduce test time and overhead. The SCCB strategy is different from the traditional test method, wherein the test access mechanism (TAM) and Scheduling are established as a virtual flattened form. We take experiments to verify the SCCB strategy based on the ITC'02 benchmarks. The experimental results show that the SCCB strategy is effective.

关键词： system-on-a-chip Design for testability Intellectual property Productivity Benchmark testing

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