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IEEE International Conference on Rehabilitation Robotics (ICORR)

作者： Sang Wan Lee Taeyoub Yi Jeong-Su Han Hyoyoung Jang Heon-Hui Kim Jin-Woo Jung Zeungnam Bien Electrical Engineering and Computer Science Department Korean Advanced Institute of Science and Technology Daejeon South Korea Core Technology Laboratory Digital Appliances Research and Development Center Samsung Electronics Company Limited Suwon South Korea Human-friendly Welfare Robot System Engineering Research Center Korean Advanced Institute of Science and Technology Daejeon South Korea Computer Engineering Department Dongguk University Seoul South Korea

This paper presents a total solution on EMG signal-based walking phase recognition for people with lower limb disability. Various environmental factors such as sensed location, walking speed, and ground inclination are taken into consideration in all the phases of signal sensing, feature extraction, feature selection, and classification. Based on analysis on fourteen well-known feature extraction methods in varying environmental situation, this paper proposes a methodology for selecting a good feature set, and then demonstrates effectiveness of the proposed approach with the classification results.

关键词： Legged locomotion Electromyography Muscles Feature extraction Environmental factors Humans Rehabilitation robotics Robots systems engineering and theory Working environment noise

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Mutiple-view object tracking using metadata

Mutiple-view object tracking using metadata

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International Conference on Wavelet Analysis and Pattern Recognition (ICWAPR)

作者： Inho Paek Changhan Park Myeongsuk Ki Kyoungju Park Joonki Paik Image Processing and Intelligent System Laboratory Department of Image Engineering Chung-Ang University Seoul South Korea Advanced Technology Research & Development Center Samsung Thales Company Limited Yongin si Gyeonggi South Korea Digital Broadcasting Research Division ETRI Electronics and Telecommunication Research Institute Daejeon South Korea Next Generation Imaging Contents Laboratory Department of Image Engineering Chung-Ang University Seoul South Korea

In this paper we present a moving object tracking method in a multiple camera tracking system using meta-data. The proposed method acquires image sequences from multiple fixed cameras without a priori camera calibration. The tracking is performed based on object's robust characteristics, such as motion, shape, color, and etc. Elements of meta-data and the optimal tracking method are selected at each frame. Because object's characteristics are affected by camera position and environmental condition, tracking method between individual cameras is selected by optimal metadata. Tracking in a single view can be divided into three classes, such as; optical flow-based moving object detector, active shape model (ASM), color correlation based detector. The proposed method matches objects to most similar object color information, by comparing meta-data and ASM. In the experiment, the proposed multi-camera tracking system is show to be robust for non-rigid objects.

关键词： Cameras Tracking Robot vision systems Surveillance Humans Biological system modeling Image analysis Robustness Object detection Active shape model

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A 55 TFLOPS simulation of amyloid-forming peptides from yeast prion Sup35 with the special-purpose computer system MDGRAPE-3

A 55 TFLOPS simulation of amyloid-forming peptides from yeas...

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2006 ACM/IEEE Conference on Supercomputing, SC'06

作者： Narumi, Tetsu Ohno, Yousuke Okimoto, Noriaki Koishi, Takahiro Suenaga, Atsushi Futatsugi, Noriyuki Yanai, Ryoko Himeno, Ryutaro Fujikawa, Shigenori Taiji, Makoto Ikei, Mitsuru Intel K.K. High Performance Molecular Simulation Team Genomic Sciences Center Innovative Nanopatterning Laboratory Topochemical Design Laboratory Frontier Research System Advanced Center for Computing and Communication Software and Solutions Group Parallel and Distributed Solutions Group

ISBN: (纸本)0769527000

We have achieved a sustained performance of 55 TFLOPS for molecular dynamics simulations of the amyloid fibril formation of peptides from the yeast Sup35 in an aqueous solution. For performing the calculations, we used the MDGRAPE-3 system - -a special-purpose computer system for molecular dynamics simulations. Its nominal peak performance was 415 TFLOPS for Coulomb force calculations;this is the highest-ever performance reported for classical molecular dynamics simulations. Amyloid fibril formation is known to be related to the occurrence of severe diseases such as Alzheimer's, Parkinson's, and Creutzfeldt-Jakob diseases. The Sup35 protein is a "yeast prion protein," which forms mini-crystals due to aggregation;it forms an effective platform for studying the formation process of amyloid fibrils. In these simulations, we first elucidate that the amyloid-forming peptides GNNQQNY aggregate at a higher frequency than non-amyloid-forming peptides SQNGNQQRG;further, the GNNQQNY peptides tend to form parallel two-stranded -sheets that would grow into a cross- amyloid nucleus. The results are consistent with those obtained experimentally. Furthermore, we could observe an early elongation of the amyloid nucleus. This result is expected to contribute toward a deeper understanding of the amyloid growth mechanism. © 2006 IEEE.

关键词： Peptides

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Filling a narrow and high aspect-ratio trench with electro-cu plating

Filling a narrow and high aspect-ratio trench with electro-c...

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作者： Chonan, Yasunori Komiyama, Takao Onuki, Jin Nagano, Takahiro Akahoshi, Haruo Itabashi, Takeyuki Saito, Tatuyuki Khoo, Khyoupin Department of Electronics and Information Systems Factory of System Science and Technology Akita Prefectual University Yurihonjyo 015-0055 Japan Department of Materials Science and Engineering Ibaraki University Hitachi 316-8511 Japan Intellexres Laboratory Hitachi 316-0015 Japan Hitachi Research Laboratory Hitachi 319-1292 Japan Advanced Research Laboratory Hitachi Ltd. Hatoyama 350-0395 Japan Hitachi Ltd. Hitachi Device Development Center 198-8512 Japan

Copper electroplating has been used for making interconnections in large-scale integration (LSI). Sub-100-nm-wide, deep trenches with aspect-ratios over 6 were fully filled by optimizing DC and pulse electroplating processes. Grain sizes of Cu of sub-100-nm wide trenches after electroplating were 70 nm for DC electroplating and 58 nm for pulse electroplating. The Cu grain sizes of Cu interconnects by DC plating after electroplating increased with the annealing temperature. © 2006 The Japan Institute of Metals.

关键词： Copper

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Ultra Low Voltage Operations in Bulk CMOS Logic Circuits with Dopant Segregated Schottky Source/Drain Transistors

Ultra Low Voltage Operations in Bulk CMOS Logic Circuits wit...

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International Electron Devices Meeting (IEDM)

作者： T. Kinoshita R. Hasumi M. Hamaguchi K. Miyashita T. Komoda A. Kinoshita J. Koga K. Adachi Y. Toyoshima T. Nakayama S. Yamada F. Matsuoka System LSI Division I Toshiba Corporation Yokohama Japan Advanced LSI Technology Laboratory Corporate Research and Development Center Toshiba Corporation Yokohama Japan

Ultra low power circuit operation is demonstrated with dopant segregated Schottky (DSS) source/drain transistors for the first time. DSS greatly improves propagation delay in multiple fan-in NAND gates at constant standby current. The delay is enhanced to 21% at 0.8V for 3-input NAND gates. Energy delay product (EDP) is improved by more than 50% with DSS at 0.8V

关键词： Low voltage CMOS logic circuits Decision support systems FETs MOSFETs Propagation delay Substrates Large scale integration Immune system CMOS technology

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Comprehensive Study on Injection Velocity Enhancement in Dopant-Segregated Schottky MOSFETs

Comprehensive Study on Injection Velocity Enhancement in Dop...

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International Electron Devices Meeting (IEDM)

作者： A. Kinoshita T. Kinoshita Y. Nishi K. Uchida S. Toriyama R. Hasumi J. Koga Advanced LSI Technology Laboratory Corporate Research and Development Center Toshiba Corporation Yokohama Japan System LSI Division I Toshiba Corporation Semiconductor Company Yokohama Japan

The carrier transport in dopant-segregated Schottky (DSS) and conventional MOSFETs was thoroughly investigated in terms of carrier injection velocity, v inj . It was found that v inj enhancement associated with the velocity overshoot enhances the current drivability in DSS, in addition to the reduction of parasitic resistance. A physical-based model was newly developed to explain the velocity overshoot behavior and reproduced the experimental data very well. Moreover, a novel type of DSS FinFET to take full advantage of the velocity overshoot was proposed and demonstrated as a primary study

关键词： MOSFETs Decision support systems Large scale integration Laboratories research and development Semiconductor process modeling FinFETs Charge carrier density Hot carrier injection Capacitive sensors

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development of a video-rate rangefinder system using light intensity modulation with scanning laser light

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systems and Computers in Japan 2006年第3期37卷 20-31页

作者： Azuma, Takeo Uomori, Kenya Nobori, Kunio Morimura, Atsushi Advanced Technology Research Laboratories Matsushita Electric Industrial Co. Ltd. Kyoto 619-0237 Japan Corporate Engineering Division Panasonic System Solutions Company Matsushita Electric Industrial Co. Ltd. Yokohama 223-8639 Japan Intelligent Processing Technology Research Laboratory Development Center Corporate Engineering Division Panasonic System Solutions Company

We have developed an active rangefinder system that can obtain depth images at video field rates by improving Carrihill's intensity ratio depth sensor. Although the depth sensor can be made at low cost, its depth precision is affected by background light, video noise, and the motion of objects. To reduce such influences, first we used a laser line pattern scanned by a rotating mirror as a light source and a camera with an optical narrow-bandpass filter - an interference filter - to overcome the background light. Second, we corrected the projected light power at the camera's peripheral field to decrease depth error there. Third, we performed inter-field median filtering of measured depths to decrease the influence of object motion. As a result, we achieved standard deviations of depths 1.4% and 2.1 % in a range of 2.2 to 3 and 3.2 to 4 m, respectively. © 2006 Wiley Periodicals, Inc.

关键词： Range finders

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Irregular buffer-zone partitioning reducing synchronization cost in SAMR

Irregular buffer-zone partitioning reducing synchronization ...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： J. Steensland Advanced Software Research and Development Sandia National Laboratory Livermore CA USA

Achieving good scalability for large simulations based on structured adaptive mesh refinement is non-trivial. Performance is limited by the partitioner's ability to efficiently use the underlying parallel computer's resources. Domain-based partitioners serve as a foundation for techniques designed to improve the scalability and they have traditionally been designed on the basis of an independence assumption regarding the computational flow among grid patches at different refinement levels. But this assumption does not hold in practice. Hence the effectiveness of these techniques is significantly impaired. This paper introduces a partitioning method designed on the true premises. The method is tested for four different applications exhibiting different behaviors. The results show that synchronization costs on average can be reduced by 75 percent. The conclusion is that the method is suitable as a foundation in general hierarchical methods designed to improve the scalability of structured adaptive mesh refinement applications.

关键词： Costs Computational modeling Scalability Grid computing Adaptive mesh refinement Concurrent computing Design methodology Electromagnetic modeling research and development Laboratories

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Ultra-low standby power (U-LSTP) 65-nm node CMOS technology utilizing HfSiON dielectric and body-biasing scheme

Ultra-low standby power (U-LSTP) 65-nm node CMOS technology ...

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Symposium on VLSI Technology

作者： N. Kimizuka Y. Yasuda T. Iwamoto I. Yamamoto K. Takano Y. Akiyama K. Imai Advanced Device Development Division NEC Electronics Corporation Limited Sagamihara Kanagawa Japan System Device Research Laboratory NEC Corporation Limited Sagamihara Kanagawa Japan

This paper reports 65-nm node ultra-low standby power CMOS technology for mobile applications, utilizing the combination of HfSiON FET and back-biasing scheme for the first time. With well-optimized channel, offset-spacer and halo conditions, physical gate length is successfully scaled down to 55 nm with excellent V/sub th/ roll-off and small DIBL, for both surface channel nFET and buried channel pFET. The record I/sub on//I/sub off/ ratio, the drive current of 510/220 /spl mu/A//spl mu/m with off-state leakage of 20/20 pA//spl mu/m, are obtained. We have also demonstrated body-biasing scheme feasibility for further subthreshold leakage (I/sub subth/) reduction. By exploiting Fermi-level-pinning effect, we have reduced the channel doping concentration and suppressed gate induced drain leakage (I/sub GIDL/) even under reverse body-biasing condition. Total standby leakage (I/sub subth/+I/sub GIDL/+I/sub g/) are reduced to 1.4/0.32 pA//spl mu/m at V/sub dd/= 0.8 V and Vb= /spl plusmn/1 V, which is the smallest value ever reported for 65nm-node LSTP.

关键词： CMOS technology Doping Boron Dielectric devices Subthreshold current Gate leakage Threshold voltage Degradation National electric code FETs

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Impact of parasitic resistance and silicon layer thickness scaling for strained-silicon MOSFETs on relaxed Si/sub 1-x/Ge/sub x/ virtual substrate

Impact of parasitic resistance and silicon layer thickness s...

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International Electron Devices Meeting (IEDM)

作者： H. Kawasaki K. Ohuchi A. Oishi O. Fujii H. Tsujii T. Ishida K. Kasai Y. Okayama K. Kojima K. Adachi N. Aoki T. Kanemura D. Hagishima M. Fujiwara S. Inaba K. Ishimaru N. Nagashima H. Ishiuchi Toshiba Corporation Semiconductor Company Yokohama Japan System LSI Division I SoC Research and Development Center Yokohama Japan Advanced LSI Technology Laboratory Toshiba Corporation Yokohama Japan Semiconductor Technology Development Group Sony Corporation Yokohama Japan

This paper discusses the root causes of the fact that only slight performance improvement of MOSFET with strained-Si substrate has been achieved in short channel region (L < 100 nm). The performance improvement in short channel region is found to deteriorate mainly due to the parasitic resistance increase and tensile stress relaxation in the strained-Si layer. In regard to the parasitic resistance and the stress relaxation in small device geometry, the scaling impacts of strained-Si layer thickness (T/sub ss/) are investigated from the viewpoint of both DC and AC characteristics. Within this work, T/sub ss/ reduction down to 5 nm improves the current drive (I/sub d/) of nFET up to 6 % (L < 50 nm) compared with conventional bulk nFET. Propagation delay time (/spl tau//sub pd/) improvement in CMOS inverter is also observed to be more than 15 %. Finally, the impurity profile optimization is proposed to improve MOSFET performance toward the 45 nm node CMOS era.

关键词： MOSFETs Impurities Silicon germanium Germanium silicon alloys Degradation Large scale integration Tensile stress Dielectric substrates Electronic mail Propagation delay

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