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检索条件"机构=SRC-CMU Center for Computer-Aided Design Department of Electrical and Computer Engineering"

共 38 条记录，以下是1-10 订阅

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Serial Bus Encoding for Low Power Application

Serial Bus Encoding for Low Power Application

引用

IEEE International Symposium on System-on-Chip

作者： Mohsen Saneei Ali Afzali-Kusha Zainalabedin Navabi Nanoelectronics Center of Excellence School of Electrical and Computer Engineering University of Tehran Tehran Iran Computer Aided Design Laboratory Electrical and Computer Engineering Department University of Tehran Tehran Iran

In this paper, we propose a low-power encoding scheme for serial buses (LESB) which can be used in SoCs. The scheme makes use of a look-up-table for encoding the input data before the parallel to serial conversion and a look-up-table after serial to parallel conversion in the decoder. Using the look-up table, the input symbols are replaced with some codewords which have some redundant bits compared to the original symbols. The serial transmission of the codewords leads to lower switching (transition) activity compared to that of the original transmission of the input symbols. The simulation results show that the when one redundant bit is used, the proposed scheme reduces the transition (switching) activity on the serial bus for uniform data more than 18% with a reduction of 11% in the throughput. More power reduction may be achieved by adding more redundant bits to original input symbols

关键词： Encoding Wires Capacitance Network-on-a-chip Energy dissipation Power engineering computing Decoding Energy consumption Application software Nanoelectronics

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Low-latency Multi-Level Mesh Topology for NoCs

Low-latency Multi-Level Mesh Topology for NoCs

引用

International Conference on Microelectronics, ICM

作者： Mohsen Saneei Ali Afzali-Kusha Zainalabedin Navabi Nanoelectronics Center of Excellence School of Electrical and Computer Engineering University of Tehran Tehran Iran Computer Aided Design Laboratory Elec. and Computer Engineering Department University of Tehran Tehran Iran

In this paper, we introduce a new topology for network on chips which is named multi-level mesh topology. The multi-level mesh topology is basically similar to the 2D-mesh with this difference that we have several meshes that have some common routers. This architecture reduces the latency and the dynamic power consumption in NoCs and can improve the communication throughput in high traffic applications. This architecture reduces the latency of 3 x 3, 5 x 5, and 7 x 7 2-level mesh architectures about 12.5%, 21.4%, and 18.5% related to mesh architecture, respectively. The results are expected to improve further if a better adaptive routing algorithm is utilized.

关键词： Network-on-a-chip Delay Network topology Wires computer interfaces computer networks Nanoelectronics Energy consumption Throughput Scalability

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A Mesochronous Technique for Communication in Network on Chips

A Mesochronous Technique for Communication in Network on Chi...

引用

International Conference on Microelectronics, ICM

作者： Mohsen Saneei Ali Afzali-Kusha Zainalabedin Navabi Nanoelectronics Center of Excellence School of Electrical and Computer Engineering University of Tehran Tehran Iran Computer Aided Design Laboratory Elec. and Computer Engineering Department University of Tehran Tehran Iran

In this paper, we propose a mesochronous scheme for communication over serial buses in network on chips (NoC). The technique, which removes metastability errors in mesochronous communications, makes use of only one strobe line with the bus. The strobe line toggles once with every frame of the data. In the suggested method, the frequencies of the transmitter and the receiver are independent with some tolerable difference. The results of HSPICE simulations in a 0.13 mum standard CMOS technology show a 3.65 Gbps as the maximum transmission bandwidth of the technique. The idea can be applied to parallel buses without any change in the control circuit.

关键词： Network-on-a-chip Clocks Integrated circuit interconnections Metastasis computer networks Frequency synchronization Bandwidth Wires Nanoelectronics design engineering

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A fuzzy-based distributed load balancing algorithm for large distributed systems

A fuzzy-based distributed load balancing algorithm for large...

引用

International Symposium on Autonomous Decentralized Systems (ISADAS)

作者： Chulhye Park J.G. Kuhl Center for Computer Aided Design and Department of Electrical and Computer Engineering University of Iowa Iowa IA USA

The paper presents a new approach to load balancing for large distributed systems. The approach characterizes the global state uncertainty inherent in a large distributed system in terms of the fuzzy set theory and presents a fuzzy-based distributed load balancing algorithm that explicitly reflects the effect of the uncertainty in the decision making process. The notion of linguistic variables is used to model state variables that have imprecise and uncertain state values and fuzzy control to estimate the amount of consistency relaxation from the states of uncertainty sources. A fuzzy-based consistency model provides a mechanism that allows each node to make flexible scheduling and state update decisions based on the estimated degree of consistency relaxation. Simulation results show that the proposed algorithm yields a better performance, substantially reduces the number of messages required, and generally transfers fewer tasks, compared to two conventional distributed load balancing algorithms.< >

关键词： Load management Uncertainty State estimation Fuzzy set theory Decision making Fuzzy control

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Stochastic performance models of parallel task systems 94

Stochastic performance models of parallel task systems

引用

Proceedings of the 1994 ACM Sigmetrics Conference on Measurement and Modeling of computer Systems

作者： Tayyab, Athar B. Kuhl, Jon G. Center for Computer Aided Design and Department of Electrical & Computer Engineering The University of Iowa Iowa City IA

ISBN: (纸本)9780897916592

This paper considers the class of parallel computations represented by directed, acyclic task graphs. These include parallel loops, multiphase algorithms, partitioning and merging algorithms, as well as any arbitrary parallel computation that can be structured by a task graph. The paper reviews the current state of the art in stochastic bound models of parallel programs and presents new stochastic bound performance models that predict the expected execution time of parallel programs on a given shared-memory multiprocessor system; and provide qualitative and quantitative description of the relationships between the structure of parallel programs, computation and synchronization behavior of the program, and architectural features of the underlying multiprocessor *** models use a new formulation based on stochastic bound analysis and are solvable for a number of distribution functions. They are applicable to shared-memory multiprocessors with significantly different architectural and synchronization performance characteristics. The accuracy of the models is validated via several measurements on two different shared-memory multiprocessor systems, the Alliant FX/2800 and the Encore Multimax. The results show the models to be quite accurate, even when some of the modeling assumptions are violated. The maximum error of prediction ranges from about 10% to under 1%.

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Experimental validation of stochastic performance models of general layered task systems

Experimental validation of stochastic performance models of ...

引用

23rd International Conference on Parallel Processing, ICPP 1994

作者： Tayyab, A.B. Kuhl, J.G. Center for Computer Aided Design Department of Electrical and Computer Engineering University of Iowa Iowa City IA 52242-1000 United States

Performance analysis of synchronization mechanisms for simple layered task systems has recently been reported. In this paper, we develop and validate performance models for general layered task systems which are applicable to a wider range of synchronization mechanisms and parallel task systems. Synchronization mechanisms considered include both strong (barrier) synchronization and weak (partial) synchronization. The models explicitly consider overheads due to synchronization waiting time and contention for shared software and hardware resources. The models are solvable for a number of commonly used task computation time distributions and are experimentally validated on two different shared-memory multiprocessors. It is shown that the task computation behavior, the amount of intertask dependencies, synchronization overheads, and throughput of the processor-memory interconnection network interact in a multi-dimensional, but predictable, way to impact overall performance. Approximate and asymptotic models are used to demonstrate these relationships, in both qualitative and quantitative terms. © 1994 IEEE.

关键词： Synchronization

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Behavioral test generation using mixed integer nonlinear programming

Behavioral test generation using mixed integer nonlinear pro...

引用

IEEE International Test Conference

作者： R.S. Ramchandani D.E. Thomas SRC-CMU Center for Computer-Aided Design Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA

This paper describes a novel technique to generate test vectors for single stuck-at faults using the behavioral description of the circuit function and the mapping from the behavior into the hardware that implements it. The test vector generation problem is formulated as a mixed integer nonlinear programming (MINLP) problem, and the test vectors are obtained by solving a series of MINLPs. The technique has been implemented and results from this approach show an order of magnitude speed up in test generation compared to existing gate-level sequential test generation tools.

关键词： Circuit testing Circuit faults Hardware design automation Sequential analysis System testing Logic testing Registers Software testing design engineering

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Automated load-independent cell library macromodeling for efficient and accurate waveform simulation

Automated load-independent cell library macromodeling for ef...

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Custom Integrated Circuits Conference (CICC)

作者： D.J. Ciplickas R.A. Rohrer SRC-CMU Research Center for CAD Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA

A novel gate-level macromodeling technique is presented. In an attempt to address the increasingly analog behavior of signals in semi-custom digital designs, the technique produces a linear transient macromodel capable of accurately predicting the gate output voltage waveform over a wide range of input and loading conditions. The macromodel is derived by analyzing SPICE generated voltage and current responses for a set of "extreme" operating conditions and is shown to exhibit good waveform prediction capability and average performance errors of approximately /spl plusmn/10%.< >

关键词： Libraries Computational modeling Signal design Voltage SPICE Semiconductor device modeling computer simulation Performance analysis Linear systems design automation

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Experimental Validation of a Performance Model for Simple Layered Task Systems

Experimental Validation of a Performance Model for Simple La...

引用

1993 International Conference on Parallel Processing, ICPP 1993

作者： Tayyab, Athar B. Kuhl, Jon G. Center for Computer Aided Design Department of Electrical and Computer Engineering University of Iowa Iowa CityIA52242 United States

ISBN: (纸本)0849389836

Performance modeling for the class of parallel computa tions structured as simple layered task systems is consid ered. Specifically studied are the effects of using different forms of inter-layer sequencing mechanisms. The paper refines and generalizes an earlier analytical performance model and presents the results of experimental validation of the model on two different multiprocessor systems. The experimental validation results show that the model is quite accurate, with average prediction errors in the range of only a few percent. Finally, the paper uses the model to investigate performance tradeoff issues for lay ered task systems using barrier versus explicit intertask sequencing mechanisms and implemented on computing systems with differing architectural features. This study shows that the relationship between the type of sequenc ing mechanism, the nature of the computation, and the features of the underlying architecture, interact in com plex ways to impact overall performance. Several inter esting and non-intuitive results are shown. © 1993 IEEE.

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Rapid simulation of substrate coupling effects in mixed-mode ICs

Rapid simulation of substrate coupling effects in mixed-mode...

引用

Custom Integrated Circuits Conference (CICC)

作者： N. Verghese D.J. Allstot S. Masui SRC-CMU Research Center for Computer Aided Design Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA Semiconductor Basic Technology Research Laboratory Nippon Steel Corporation Kanagawa Japan

Asymptotic waveform evaluation (AWE) techniques have been used to develop macromodels that allow accurate and efficient simulation of substrate-related parasitic electrical coupling effects using a modified version of SPICE3. While achieving comparable accuracy to a mixed device-circuit simulator (PISCES IIB), simulation time is reduced by several orders of magnitude. The macromodeling technique can be extended to simulate noise coupling in a VLSI chip, in contrast to conventional device-circuit simulators.

关键词： Substrates Coupling circuits Circuit simulation Crosstalk Semiconductor device noise Voltage Circuit noise Maxwell equations Computational modeling CMOS technology

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