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THE USE OF PROPULSION SHAFT TORQUE AND SPEED MEASUREMENTS TO IMPROVE THE LIFE-CYCLE PERFORMANCE OF UNITED-STATES NAVAL SHIPS

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NAVAL ENGINEERS JOURNAL 1992年第6期104卷 43-57页

作者： HUNDLEY, LL TSAI, SJ Lowry L. Hundley:is a project manager/instrumentation engineer with the Hydromechanics Department at the Carderock Division Naval Surface Warfare Center. His 25 years of experience include the planning and directing of sea trials on Navy Coast Guard and commercial ships. Mr. Hundley has been responsible for assessing and improving the methods used to collect and analyze ship powering and maneuvering data. He received a B.S. degree in electrical engineering from Virginia Polytechnic Institute in 1967 and is a member of ASNE. Shou-Jen Tsai:is a naval architect with the Full-Scale Trials Branch Ship Hydromechanics Department at Carderock Division Naval Surface Warfare Center. His 20 years of experience include ship repair and computer-aided ship design and performance analysis. He is a licensed marine engineer with 5 years of shipboard operation experience. Mr. Tsai received a B.S. degree in naval architecture from Taiwan Provincial College of Marine and Oceanic Technology in 1970 and a master's degree in ocean engineering from Stevens Institute of Technology in 1980.

This paper describes the benefits of having permanent torsionmeters installed on the main propulsion shafting of U. S. naval ships. Propulsion shaft torque and speed measurements provide ship operators with accurate knowledge of the ship's powering condition at any given time. This information can be compared with baseline data to reveal degradation in the ship's powering performance. Performance trends produced by observations over an extended period of time can be utilized to forecast the point at which corrective action should be taken. The timely implementation of necessary corrective action can significantly decrease the ship's operating cost by reducing fuel consumption while minimizing excessive wear on the ship's machinery and, in all probability, extend the ship's service life. The value of accurate powering measurements is discussed in conjunction with (1) the accumulation and removal of hull and propeller marine growth, (2) single shaft operation, and (3) ships equipped with controllable pitch propellers. An overview of modern torsionmeters is presented based on literally hundreds of sea trials involving personnel from the Carderock Division. Naval Surface Warfare center. Development of an overall program is suggested to ensure that (1) only accurate and reliable torsionmeters are installed on U. S. naval ships, (2) the meters are properly maintained and monitored, and (3) full utilization is made of the data obtained and of the baseline data currently available.

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AN EFFICIENT ALGORITHM FOR PARAMETRIC FAULT SIMULATION OF MONOLITHIC ICS

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IEEE TRANSACTIONS ON computer-aided design OF INTEGRATED CIRCUITS AND SYSTEMS 1991年第8期10卷 1049-1058页

作者： STROJWAS, AJ DIRECTOR, SW SRC-CMU Center for Computer-Aided Design Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA

An efficient methodology for performing fault simulation experiments as a part of an IC failure diagnosis system is described. The basis of this methodology is the use of regression models that relate IC performances directly to process disturbances inherent in all IC fabrication processes. An efficient algorithm for establishing the structure of such models based upon data obtained from coupled process and circuit simulators is developed. This new self-organization algorithm, which has a multilayer structure of Rosenblatt's perceptron type, selects a minimum number of significant input parameters and automatically establishes an optimum order polynomial regression model. The algorithm belongs to the class of the recently fashionable artificial neural network approaches. The algorithm has been implemented in a software tool called MUlti-layer REGression (MULREG), which has been tested successfully on a large number of examples.

关键词： Integrated circuit modeling Circuit faults Circuit simulation Fault diagnosis Fabrication Coupling circuits Polynomials Regression tree analysis Artificial neural networks Multi-layer neural network

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STATISTICAL CONTROL OF VLSI FABRICATION PROCESSES - A SOFTWARE SYSTEM

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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING 1988年第2期1卷 72-82页

作者： SHYAMSUNDAR, CR MOZUMDER, PK STROJWAS, AJ SRC-CMU Center for Computer-Aided Design Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA

For pt.I see ibid., vol.1, no.2, p.62-71, 1988. The algorithms used to implement the cmu-CAM statistical control system for VLSI integrated circuit fabrication are presented. The cmu-CAM system performs three major operations: modeling; quality control; and feed-forward control. In order to increase the efficiency of modeling and control, the problem is decomposed using statistical factorization techniques. Algorithms for process modeling and algorithms used in quality control and feed-forward control are described. The cmu-CAM system performs profit maximization through statistical process control. Its capabilities are illustrated by a number of computational examples.< >

关键词： Very large scale integration Fabrication Software systems Process control Control systems Software algorithms Quality control Feeds Clustering algorithms Software performance

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STATISTICAL CONTROL OF VLSI FABRICATION PROCESSES - A FRAMEWORK

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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING 1988年第2期1卷 62-71页

作者： MOZUMDER, PK SHYAMSUNDAR, CR STROJWAS, AJ SRC-CMU Center for Computer-Aided Design Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA

A general framework for statistical control of VLSI (very large-scale integration) fabrication processes is given along with the architectural description of a software system that can be used for monitoring, diagnosis, and quality/quantity control of computer-aided integrated circuit manufacture. The task of process control is formulated as one of profit maximization, and the associated objective function and the constraints are developed for a number of manufacturing scenarios. The IC fabrication process is modeled as a stochastic system and the necessary conditions for efficient statistical control of VLSI fabrication processes are described.< >

关键词： Very large scale integration Fabrication Control systems Integrated circuit modeling Large scale integration Software systems computerized monitoring computer aided manufacturing Integrated circuit manufacture Process control

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PLACEMENT BY SIMULATED ANNEALING ON A MULTIPROCESSOR

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IEEE TRANSACTIONS ON computer-aided design OF INTEGRATED CIRCUITS AND SYSTEMS 1987年第4期6卷 534-549页

作者： KRAVITZ, SA RUTENBAR, RA SRC-CMU Center for CAD Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA

Physical design tools based on simulated annealing algorithms have been shown to produce results of extremely high quality, but typically at a very high cost in execution time. This paper selects a representative annealing application--standard cell placement--and develops multiprocessor-based annealing algorithms for placement. A taxonomy of possible multiprocessor decompositions of annealing algorithms is presented which divides decomposition schemes into two broad classes: those which divide individual moves into subtasks and distribute them across cooperating processors, and those which perform complete moves in parallel. It is shown that the choice of multiprocessor annealing strategy is influenced by temperature; in particular, the paper introduces the idea of adaptive strategies that dynamically change the parallel decomposition scheme to achieve maximum speedup as the annealing task progresses through each temperature regime. Implementations of three parallel placement strategies are described for an experimental shared-memory multiprocessor. Practical speedups are achieved over a serial version of the algorithm, and it is shown that an adaptive strategy which switches between two parallel decompositions at the optimal temperature yields speedup significantly better than any single strategy approach. Models are developed to account for the observed performance, and to predict the crossover points for switching strategies.

关键词： Simulated annealing Temperature Very large scale integration Costs Taxonomy Switches Predictive models Wiring Delay

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A NEW APPROACH TO HIERARCHICAL AND STATISTICAL TIMING SIMULATIONS

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IEEE TRANSACTIONS ON computer-aided design OF INTEGRATED CIRCUITS AND SYSTEMS 1987年第6期6卷 1039-1052页

作者： BENKOSKI, J STROJWAS, AJ SRC-CMU Center for CAD Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA

This paper describes a new approach for timing analysis in general and, more specifically, for statistical timing analysis. A methodology based upon the utilization of the design hierarchy for circuit partitioning and building of the simulation hierarchy was developed. The logic and timing behaviors of the blocks resulting from the partitioning are dissociated and modeled separately. The logic model is represented by an equivalent finite state machine while an automated characterization process extracts the timing data from multiple circuit simulations in order to build a parametric timing model. These models provide the basis of an event-driven hierarchical timing simulator which can be used as a stand-alone tool but also as a front end for statistical timing analyses. Both the nominal and the statistical simulators have been implemented within STAT! (Statistical Timing Analysis Tool), and the results obtained for a few test cases are presented here.

关键词： Timing Circuit simulation Analytical models Logic circuits Computational modeling Circuit testing Logic design design automation Buildings Automata

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REALISTIC YIELD SIMULATION FOR VLSIC STRUCTURAL FAILURES

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IEEE TRANSACTIONS ON computer-aided design OF INTEGRATED CIRCUITS AND SYSTEMS 1987年第6期6卷 965-980页

作者： CHEN, I STROJWAS, AJ SRC-CMU Center for CAD Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA

This paper presents a methodology for determining the probability of structural failures for VLSI circuits. An analytically based approach is used to perform simulations accurately and efficiently. This approach considers the specific IC layout and accounts for most of the fault mechanisms caused by global geometrical variations and local defects. A hierarchical model is proposed to describe the defect statistics including clustering. Strict analytical methods are used to find probabilities of failure for simple layout patterns. Then, the probability of failure for macrocells are calculated hierarchically. This methodology has been implemented in a CAD tool called RYE (Realistic Yield Evaluator). To demonstrate the effectiveness of this tool, the simulation results of several examples and the CPU time comparisons with Monte Carlo methods are also presented in this paper.

关键词： Circuit simulation Probability Very large scale integration Circuit analysis Performance analysis Analytical models Integrated circuit layout Circuit faults Statistics Failure analysis

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A SCANLINE DATA STRUCTURE PROCESSOR FOR VLSI GEOMETRY CHECKING

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IEEE TRANSACTIONS ON computer-aided design OF INTEGRATED CIRCUITS AND SYSTEMS 1987年第5期6卷 780-794页

作者： CARLSON, EC RUTENBAR, RA SRC-CMU Center for CAD Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA

This paper proposes an architecture to support VLSI geometry checking tasks based on scanline algorithms. Rather than recast the entire verification task in hardware, we identify primitives around which geometry checking tools can be built, and examine the feasibility of accelerating two of these critical primitives. We focus on the operations of Boolean combinations of mask layers, and region numbering within a mask layer. Unlike previous proposals for special hardware (e.g., bit map processors), this architecture operates on a more realistic representation of masks: a sorted stream of possibly oblique edges. The architecture can be viewed as directly interpreting the operators that manipulate the relevant scanline data structures. We show how the edge computations in these two algorithms can be restructured into the form of a single, shared hardware pipeline. Data from a simulation of this processor suggests that, relative to the specific software functions it is intended to replace, the scanline processor can reduce computation time significantly. In particular, simulations of one possible implementation for this processor yield speedups of three orders of magnitude for Manhattan mask data, degrading gracefully to speedups of two orders of magnitude for highly oblique mask data.

关键词： Data structures Very large scale integration Geometry Hardware computer architecture Computational modeling Acceleration Proposals Pipelines Degradation

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A METHODOLOGY FOR WORST-CASE ANALYSIS OF INTEGRATED-CIRCUITS

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IEEE TRANSACTIONS ON computer-aided design OF INTEGRATED CIRCUITS AND SYSTEMS 1986年第1期5卷 104-113页

作者： NASSIF, SR STROJWAS, AJ DIRECTOR, SW Department Electrical and Computer Engineering Research Center for Computer-Aided Design Carnegie Mellon University Pittsburgh PA USA

Worst-case analysis is one of the most often used techniques for verifying that the sensitivity of integrated circuit (IC) performances to changes in manufacturing conditions is minimized. However, worst-case analysis is often carried out in terms of a correlated set of parameters, which results in a design that is unnecessarily pessimistic. This paper presents a new approach to the worst-case analysis of integrated circuits that results in more realistic estimates of variations in device and circuit performances. In particular, worst-case analysis is performed in terms of a set of statistically independent process disturbances. A software package for worst-case analysis is described and illustrated by a number of examples. The results of the proposed worst-case analysis method are compared to Monte Carlo simulations.

关键词： Circuit analysis Performance analysis Fluctuations Power dissipation Circuit simulation Integrated circuit manufacture Software packages Manufacturing processes Performance evaluation Delay lines

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VLSI CAD tool integration using the Ulysses environment

VLSI CAD tool integration using the Ulysses environment

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23rd ACM/IEEE design Automation Conference, DAC 1986

作者： Bushnell, Michael L. Director, S.W. SRC-CMU Research Center for Computer-Aided Design Department of Electrical and Computer Engineering Carnegie-Mellon University PittsburghPA15213 United States

ISBN: (纸本)0818607025

Ulysses is a VLSI CAD environment which effectively addresses the problems associated with CAD tool integration. Specifically, Ulysses allows the integration of CAD tools into a design automation system, the codification of a design methodology, and the representation of a design space. Ulysses keeps track of the progress of a design and allows exploration of the design space. The environment employs artificial intelligence techniques, functions as an interactive expert system, and interprets descriptions of design tasks encoded in the scripts language. An example of an integrated circuit layout design task is provided. The use of Ulysses in performing this task is discussed in detail. © 1986 IEEE.

关键词： Expert systems

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