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Serial block processing for multi-code WCDMA frequency domain equalization

Serial block processing for multi-code WCDMA frequency domai...

引用

IEEE Conference on Wireless Communications and Networking

作者： D. Lo Iacono E. Messina C. Volpe A. Spalvieri Advanced System Technology STMicroelectronics France Dipartimento di Elettronica e Informazione Politecnico di Milano Italy

This paper presents an efficient implementation of a frequency domain linear equalizer for WCDMA systems. A significant complexity reduction with respect to traditional equalizers can be achieved by means of frequency domain block processing. After deriving the analytical formulation of the equalizer coefficients, it is shown that the performance of the frequency domain equalizer (FDE) is substantially equivalent to that of the classical time domain equalizer (TDE) over a wide range of operating conditions so that no penalty has to be paid for the complexity reduction. Starting from a pure parallel implementation of the FDE, it is shown that block processing for multi-code downlink WCDMA can be conveniently performed in a serial fashion, through properly reusing small processing elements while exploiting the pipeline in order to reduce the subsequent latency overhead.

关键词： Multiaccess communication Frequency domain analysis Equalizers Delay Multiple access interference Downlink Pipelines Intersymbol interference Transversal filters Performance analysis

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Frame concealment for H.264/AVC decoders

Frame concealment for H.264/AVC decoders

引用

IEEE International Conference on Consumer Electronics (ICCE)

作者： P. Baccichet D. Bagni A. Chimienti L. Pezzoni F. Rovati IEIIT Consiglio Nationale delle Ricerche Torino Italy Advanced System Technology Laboratories STMicroelectronics Agrate Italy

We propose a novel technique for H.264/AVC video decoders, to perform the concealment of a whole frame in case of loss due to network errors. The application scenario is low resolution video streaming over a packed-sw... 详细信息

关键词： Automatic voltage control Decoding Filtering Streaming media Optical buffering Optical filters Optical network units Kernel Interpolation Robustness

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Natural images classification by multiple pixel analysis

Natural images classification by multiple pixel analysis

引用

IEEE International Conference on Consumer Electronics (ICCE)

作者： F. Naccari S. Battiato A. Capra S. Cariolo A. Castorina Advanced System Technology Catania Laboratory STMicroelectronics Italy Dipartmento di Matematica ed Informatica Universita Catania Italy

This work describes an algorithm aimed at performing an automatic natural scene image classification. It is based on a combined analysis of chromatic and spatial features of the pixels, for the recognition of landscape and portrait scenes. Quantitative results are also presented and show the effectiveness of the combined analysis proposed. Various image processing applications can easily take advantage of the proposed solution.

关键词： Image classification Pixel Image analysis Layout Skin Image color analysis Humans Image databases Image segmentation Vegetation mapping

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Low Power Design for Embedded systems:Today and Tomorrow

Low Power Design for Embedded Systems:Today and Tomorrow

引用

2005 6th International Conference on ASIC

作者： Roberto Zafalon STMicroelectronics Advanced System Technology-R&I Via Olivetti 220041 Agrate BrianzaItaly

ISBN: (纸本)0780392108

*** The rapid advances of nomadic computing applications, pushed by the fast-evolving technology for wireless network connectivity(Wireless LAN 802.11/WiFi standards,3G UMTS,WiMAX metropolitan area networks,etc.) and by the need to provide personalized, context-aware multimedia services,are driving the evolution of mobile terminals into complex multimedia platforms whose integration is limited by the max power *** application's requirements for higher computation features must be met by increasing performance of SoC architectures,while at the same time ensuring energy efficiency and high flexibility on a wide range of application ***'s highly complex

关键词： power analysis low power design leakage power system-level energy optimization

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PERFORMANCE EVALUATION OF UGS GRANT SYNCHRONIZATION FOR 802.16

PERFORMANCE EVALUATION OF UGS GRANT SYNCHRONIZATION FOR 802....

引用

2005全球移动通信大会

作者： Jonny SUN Advanced System Technology Telecom Lab (Beijing)STMicroelectronics No.49 Zhichun Road Haidian District 100080 Beijing CN

IEEE 802.16 family, designated as a suite of air interfaces for fixed, portable and even mobile BWA (Broadband Wireless Access) systems, defines UGS (Unsolicited Granted Service) to support real-time service flows that generate fixed-sized data packets at periodic intervals. To cater for the flow's delay and bandwidth requirements, fixed-sized unsolicited data grants are issued at the same periodic intervals. However, when these two periodic behaviors are synchronization mismatch, a possible delay may be introduced at transmitter side. Although this delay can be reduced by a form of Grant Synchronization mechanism, the operation is possible to collide with the scheduled transmission when multiple flows are present. In this paper, we model the IEEE 802.16 MAC layer protocol and evaluate the performance of UGS Grant Synchronization using NS2 (Network Simulator). Some scheduling algorithms are given to resolve the collision. A conclusion is derived based on the simulation results.

关键词： UGS PERFORMANCE EVALUATION OF UGS GRANT SYNCHRONIZATION FOR 802.16 FDD

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AES power attack based on induced cache miss and countermeasure

AES power attack based on induced cache miss and countermeas...

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International Conference on Information technology: Coding and Computing (ITCC)

作者： G. Bertoni V. Zaccaria L. Breveglieri M. Monchiero G. Palermo Advanced System Technology STMicroelectronics Agrate Milan Italy Dipartimento di Elettronica e Informazione Politecnico di Milano Milan Italy

This paper presents a new attack against a software implementation of the advanced Encryption Standard. The attack aims at flushing elements of the SBOX from the cache, thus inducing a cache miss during the encryption phase. The power trace is then used to detect when the cache miss occurs; if the miss happens in the first round of the AES then the information can be used to recover part of the secret key. The attack has been simulated using the Wattch simulation framework and a simple software implementation of AES (using a single table for the SBOX). The attack can be easily extended to more sophisticated versions of AES with more than one table. Eventually, we present a simple countermeasure which does not require randomization.

关键词： Cryptography Delay Software standards Cache memory Energy consumption Timing Information technology Computer architecture

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Image registration method for consumer devices

Image registration method for consumer devices

引用

IEEE International Conference on Consumer Electronics (ICCE)

作者： I. Guarneri M. Guarnera G. Lupica S. Casale Advanced System Technology Imaging Group Catania Laboratory STMicroelectronics Italy Department of Computer Science and Telecommunication Electronics Engineering University of Catania Italy

A projective image registration algorithm, oriented to consumer devices, is proposed. It exploits a "multi-resolution feature based method" for estimating the projective parameters through a 2D Daubechies discrete wavelet transform (DWT). The algorithm has been fully tested with real image sequences acquired by CMOS sensors and compared to other registration techniques. The obtained results highlight the accuracy of the registration parameters.

关键词： Image registration Discrete wavelet transforms CMOS image sensors Testing Layout Wavelet coefficients Image sequences Optical distortion Noise reduction Filtering

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Energy-aware system-on-chip for 5 GHz wireless LANs

引用

15th International Workshop on Integrated Circuit and system Design: Power and Timing Modeling, Optimization and Simulation, PATMOS 2005

作者： Bisdounis, Labros Blionas, Spyros Macii, Enrico Nikolaidis, Spiridon Zafalon, Roberto INTRACOM S.A. Markopoulo Ave. GR-19002 Peania Athens Greece Dipartimento di Automatica e Informatica Politecnico di Torino 1-10129 Torino Italy Department of Physics Aristotle University of Thessaloniki GR-54124 Thessaloniki Greece STMicroelectronics Advanced System Technology 1-20041 Agrate Brianza Milan Italy

ISBN: (纸本)3540290133

This paper presents the realization of an energy-aware system-on-chip that implements the baseband processing as well as the medium access control and data link control functionalities of a 5 GHz wireless system. It is compliant with the HIPERLAN/2 standard, but it also covers critical functionality of the IEEE 802.11a standard. Two embedded processor cores, dedicated hardware, on-chip memory elements, as well as advanced bus architectures and peripheral inter-faces were carefully combined and optimized for the targeted application, leading to a proper trade-off of silicon area, flexibility and power consumption. A system-level low-power design methodology has been used, due to the fact that power consumption is the most critical parameter in electronic portable system design. The 17.5 million-transistor solution was implemented in a 0.18 0m CMOS pro-cess and performs baseband processing at data rates up to 54 Mbit/s, with average power consumption of about 550 mW. © Springer-Verlag Berlin Heidelberg 2005.

关键词： Local area networks

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Flexible multi-bank architecture for power-constraint 3GPP-HSPDA deinterleaving applications

Flexible multi-bank architecture for power-constraint 3GPP-H...

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10th International Symposium on Integrated Circuits, Devices and systems, ISIC-2004: Integrated systems on Silicon - Proceedings

作者： Imbesi, Pasquale Speziali, Filippo Wellig, Armin Zory, Julien Advanced System Technology STMicroelectronics Catania Italy Advanced System Technology STMicroelectronics Geneva Switzerland

ISBN: (纸本)9810517874

Interleaving is a key component of nowadays wireless systems that is used to protect the communication against burst errors. The interleaver block breaks the temporal correlation of successive samples by reshuffling them prior to transmission. In state-of-the-art solutions, this memory intensive operation is both power consuming due to frequent accesses to large memories and area inefficient due to large adaptation buffers. In this paper, we propose a novel interleaved de-interleaving scheme which significantly reduces the overall number of memory accesses in the presence of several time-aligned physical channels. A flexible multi-bank architecture is employed to achieve low-power high-throughput de-interleaving. The high-speed data packet access (HSDPA) as defined in 3GPP serves as target application, where energy reductions of up to 60% with negligible logic overhead is observed for stmicroelectronics' 0.13 μm CMOS process technology.

关键词： Data communication systems

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Joint Gaussian noise reduction and defects correction in raw digital images

Joint Gaussian noise reduction and defects correction in raw...

引用

6th Nordic Signal Processing Symposium (NORSIG 2004)

作者： Bosco, A Bruna, A Santoro, G Vivirito, P STMicroelectronics AST-Advanced System Technology Catania Lab - Imaging Group

ISBN: (纸本)951227065X

In dim light conditions, digital images are prone to high noise levels, especially if a low cost imager is used. Gaussian and impulsive noises are the most likely to appear. Furthermore, defective, stuck pixels are quite unpleasant as well. In low illumination conditions, impulsive noise is particularly annoying;because of the high signal amplification, more than one defective pixel is likely to show tip in the filter mask at the same time. A spatial filter is proposed, capable of removing Gaussian noise. impulsive noise and stuck pixels by using the same processing kernel.

关键词： Gaussian noise (electronic)

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