we propose a new EPON MAC protocol guaranteeing fairness among users by allocating excess bandwidth proportional to their subscription rates, The novelty of the protocol is in the use of scalable per-subscription-rate...
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we propose a new EPON MAC protocol guaranteeing fairness among users by allocating excess bandwidth proportional to their subscription rates, The novelty of the protocol is in the use of scalable per-subscription-rate-queuing with round-robin scheduling and packet reclassification at ONU.
This paper describes a low complexity Variable Bit-Rate (VBR) control method that achieves excellent and constant visual quality for single-pass, real time MPEG-2 encoding in DVD recorders. The bitrate is controlled i...
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This paper describes a low complexity Variable Bit-Rate (VBR) control method that achieves excellent and constant visual quality for single-pass, real time MPEG-2 encoding in DVD recorders. The bitrate is controlled in a very accurate way. The algorithm runs in software on a Very Long Instruction Word (VLIW) processor by using less than 3 Millions of clock cycles.
We propose a new EPON MAC protocol guaranteeing fairness among users by allocating excess bandwidth proportional to their subscription rates. The novelty of the protocol is in the use of scalable per-subscription-rate...
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A noise reduction filter for full-frame data imaging devices was discussed. Fixed Pattern Noise and Temporal Noise are removed by analyzing a series of lines placed at the top of the imager. It allows to perform noise...
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A noise reduction filter for full-frame data imaging devices was discussed. Fixed Pattern Noise and Temporal Noise are removed by analyzing a series of lines placed at the top of the imager. It allows to perform noise levels estimation quickly and to improve significantly the quality of the source noisy video.
Summary form only given. Semiconductors will play a key role to drive the technological evolution in the next 20 years. We already possess many of the technologies that will deeply change our scenario, among which we ...
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Summary form only given. Semiconductors will play a key role to drive the technological evolution in the next 20 years. We already possess many of the technologies that will deeply change our scenario, among which we can mention nanotechnologies, bioelectronics, photonics. The central role of integrated circuits in the economy will grow stronger and stronger in the future, starting from the convergence between storage, security, video, audio, mobility and connectivity. systems are converging and ICs are more and more converging with systems. The fundamental issue is how to translate knowledge and competence coming from different fields into single architectures. The key factor to win this challenge is to build the right culture. This means to be able to build an organisation for innovation, with the right mix of creativity, personal initiative and execution skills.
In this paper a high-level SoC architecture exploration of DMT (Discrete Multitone) VDSL transceivers (Very high speed Digital Subscriber Line) is presented. A flexible and complete virtual platform was developed for ...
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In this paper a high-level SoC architecture exploration of DMT (Discrete Multitone) VDSL transceivers (Very high speed Digital Subscriber Line) is presented. A flexible and complete virtual platform was developed for the purpose, exploiting the paradigm of "orthogonalization of concerns" (functionality independent from architecture) in the framework of Cadence VCC system level design tool. An accurate processor model, obtained through the back-annotation of profiling results on a target DSP core, allowed the exploration of different HW/SW partitioning and the study of the computational units required. A transaction-accurate VCC bus model was developed for the investigation of the on-chip bus architecture and its relevant parameters dimensioning.
Today, the advent of the multi-million transistor chip offers the opportunity to provide more integrated functionalities into a single silicon die. This is both a clear advantage to improve existing products and a har...
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Today, the advent of the multi-million transistor chip offers the opportunity to provide more integrated functionalities into a single silicon die. This is both a clear advantage to improve existing products and a hard challenge to cope with. Unfortunately, today's available design methodologies and tools are not sufficiently advanced to exploit the full potential of such large silicon flexibility. On one hand, the design of complex system-on-chip requires new tools for the analysis and optimization of embedded software, which should extend the standard tool chain consisting of complier, debugger and simulator. On the other hand, the development of such tool chain for a new microprocessor requires a substantial time effort which is no more compatible with actual market dynamics. In stmicroelectronics, we developed a technology which tries to tackle such a double-face problem by adding several retargetability features to a standard tool chain and by providing new tools for code analysis.
This paper proposes an analytical study and a bit-error-rate (BER) analysis for antenna verification algorithm to be used in closed loop mode one antenna diversity. The purpose of such algorithm, envisaged in 3GPP, is...
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This paper proposes an analytical study and a bit-error-rate (BER) analysis for antenna verification algorithm to be used in closed loop mode one antenna diversity. The purpose of such algorithm, envisaged in 3GPP, is to improve the receiver performance in the case when the BTS applies a wrong phase rotation to antenna 2 because of a demodulation error on the reverse-link. After a deep analytical description of this algorithm, a performance analysis is done for comparing closed loop mode one scheme among the perfect-feedback case (uplink BER=0) and the case when the uplink is affected by a certain error rate, with and without antenna diversity.
The paper describes an image generation pipeline able to realize a "viewfinder". The viewfinder of a typical handset device allows user to track in real time the scene under detection. The pipeline is compos...
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The paper describes an image generation pipeline able to realize a "viewfinder". The viewfinder of a typical handset device allows user to track in real time the scene under detection. The pipeline is composed by a set of blocks implementing demosaicing and image enhancement algorithms with new and efficient techniques able to reduce considerably the computational overhead. Experiments show how modest computational resources can be coupled with acceptable perceived image quality for this particular target.
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