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Block processing engine for high-throughput wireless communications

Block processing engine for high-throughput wireless communi...

引用

2nd International Symposium on Wireless Communications systems (ISWCS 2005)

作者： Lo Iacono, D Zory, J Messina, E Piazzese, N Advanced System Technology Group STMicroelectronics

ISBN: (纸本)078039206X

This paper presents the Block Processing Engine (BPE), a programmable architecture specifically suited for high-throughput wireless communications. Thanks to a high degree of parallelism and a consistent use of pipelined processing, the BPE can satisfy the stringent real-time constraints imposed by emerging technologies. Its efficiency has been proven through the implementation of a dual standard frequency domain equalizer supporting 3GPP HSDPA and IEEE 802.11a.

关键词： ASIP VLIW WLAN HSDPA FDE

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Fast method for noise level estimation and denoising

Fast method for noise level estimation and denoising

引用

23rd Annual International Conference on Consumer Electronics (ICCE)

作者： Bosco, A Bruna, A Messina, G Spampinato, G STMicroelectronics Advanced System Technology Imaging Group Catania Lab. Italy

This paper describes a novel technique for fast noise level estimation that can be used both in spatial and temporal filters to tune the filtering strength. The method has been validated by integrating it in a denoisi... 详细信息

ISBN: (纸本)0780388380

关键词： Gaussian noise (electronic)

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Block processing engine for high-throughput wireless communications

Block processing engine for high-throughput wireless communi...

引用

International Symposium on Wireless Communication systems (ISWCS)

作者： D. Lo Iacono J. Zory E. Messina N. Piazzese Advanced System Technology Group STMicroelectronics Italy

This paper presents the block processing engine (BPE), a programmable architecture specifically suited for high-throughput wireless communications. Thanks to a high degree of parallelism and a consistent use of pipelined processing, the BPE can satisfy the stringent real-time constraints imposed by emerging technologies. Its efficiency has been proven through the implementation of a dual standard frequency domain equalizer supporting 3GPP HSDPA and IEEE 802.11a.

关键词： Engines Wireless communication Multiaccess communication Application specific processors Parallel processing Application specific integrated circuits Digital signal processing Frequency domain analysis Equalizers Wireless LAN

来源：评论

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Fast method for noise level estimation and denoising [image processing example]

Fast method for noise level estimation and denoising [image ...

引用

IEEE International Conference on Consumer Electronics (ICCE)

作者： A. Bosco A. Bruna G. Messina G. Spampinato Advanced System Technology Imaging Group Catania Laboratory STMicroelectronics Italy

This work describes a novel technique for fast noise level estimation that can be used both in spatial and temporal filters to tune the filtering strength. The method has been validated by integrating it in a denoisin... 详细信息

关键词： Noise level Noise reduction Histograms Gaussian noise Filters Sensor arrays Filtering Gaussian distribution Pixel Colored noise

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Image registration method for consumer devices

Image registration method for consumer devices

引用

IEEE International Conference on Consumer Electronics (ICCE)

作者： I. Guarneri M. Guarnera G. Lupica S. Casale Advanced System Technology Imaging Group Catania Laboratory STMicroelectronics Italy Department of Computer Science and Telecommunication Electronics Engineering University of Catania Italy

A projective image registration algorithm, oriented to consumer devices, is proposed. It exploits a "multi-resolution feature based method" for estimating the projective parameters through a 2D Daubechies discrete wavelet transform (DWT). The algorithm has been fully tested with real image sequences acquired by CMOS sensors and compared to other registration techniques. The obtained results highlight the accuracy of the registration parameters.

关键词： Image registration Discrete wavelet transforms CMOS image sensors Testing Layout Wavelet coefficients Image sequences Optical distortion Noise reduction Filtering

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Joint Gaussian noise reduction and defects correction in raw digital images

Joint Gaussian noise reduction and defects correction in raw...

引用

6th Nordic Signal Processing Symposium (NORSIG 2004)

作者： Bosco, A Bruna, A Santoro, G Vivirito, P STMicroelectronics AST-Advanced System Technology Catania Lab - Imaging Group

ISBN: (纸本)951227065X

In dim light conditions, digital images are prone to high noise levels, especially if a low cost imager is used. Gaussian and impulsive noises are the most likely to appear. Furthermore, defective, stuck pixels are quite unpleasant as well. In low illumination conditions, impulsive noise is particularly annoying;because of the high signal amplification, more than one defective pixel is likely to show tip in the filter mask at the same time. A spatial filter is proposed, capable of removing Gaussian noise. impulsive noise and stuck pixels by using the same processing kernel.

关键词： Gaussian noise (electronic)

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Fully-integrated WCDMA direct conversion SiGeC BiCMOS receiver

Fully-integrated WCDMA direct conversion SiGeC BiCMOS receiv...

引用

Proceedings of the 2004 IEEE Bipolar/BiCMOS Circuits and technology Meeting

作者： Garcia, Patrice Pellat, Bruno Blanc, Jean-Pierre Persechini, Pascal Knopik, Vincent Baud, Laurent Goussin, Franck Thevenet, Davy Majcherczak, Sandrine Reaute, Fabien Richard, Oliver Conti, Patrick Szelag, Bertrand Belot, Didier STMicroelectronics Analog RF Design Group CR and D 850 Rue Jean Monnet 38926 Crolles France STMicroelectronics Advanced System Technology 39 Ch. du champs des filles CH-1228 Geneve Switzerland

This paper describes a WCDMA direct conversion receiver which has been integrated in a BiCMOS SiGe-Carbon process featuring 0.25um/fT=60GHz bipolar transistor. This receiver includes integrated RF-Front-End with local oscillator quadrature generator, 5th order Butterworth analog baseband lowpass filter (LPF) and variable gain amplifier (VGA), cut-off frequency calibrator, DAC for DC-offset calibration, serial bus interface and voltage and current reference generators. In the high/low gain modes this device consumes 25mA and 20mA respectively with 2.7V power supply. The die is wire bounded directly on the validation board. Within the receive band, the measurements show 51dB of overall gain, NF=5dB, IIP3=-9dBm, ICP1=-15dBm. ©2004 IEEE.

关键词： Code division multiple access

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Low-power system-on-chip architecture for wireless LANs

Low-power system-on-chip architecture for wireless LANs

引用

作者： Bisdounis, L. Dre, C. Blionas, S. Metafas, D. Tatsaki, A. Ieromnimon, F. Macii, E. Rouzet, P. Zafalon, R. Benini, L. INTRACOM S.A. Technical Division 19.5 Km Markopoulo Ave. GR-19002 Peania Athens Greece Dipartimento di Automatica Politecnico di Torino Corso Duca degli Abruzzi 24 I-10129 Torino Italy STMicroelectronics Advanced System Technology Broadband Wireless LAN Group Chemin du Champ des Filles 39 CH-1228 Plan-les-Quates-Geneve Switzerland STMicroelectronics Advanced System Technology Low-Power System Design Group Via C. Olivetti 2 I-20041 Agrate Brianza Milano Italy Dipto. di Elettronica Informatica Universitá di Bologna Viale Risorgimento 2 I-40136 Bologna Italy

The authors present the architecture of a low-power system-on-chip (SoC) that implements baseband processing as well as the medium access control and data link control functionalities of a 5 GHz wireless system. The design is based on the HIPERLAN/2 wireless LAN standard, but it also covers critical processing requirements of the IEEE 802.11a standard. The options, constraints and motivations for the taken design decisions are presented, and the followed design steps, starting from the system specifications up to the architecture definition and the system implementation, are explained. The system's functionality covers both mobile terminal and access point devices. A critical design task in such systems is the assignment of the target system's tasks on the different types of processing elements available. Processor cores, dedicated hardware as well as memory elements and advanced bus architectures are used in order to achieve the target implementation. The architecture is targeted for a low-power SoC platform, due to the fact that power consumption is a critical parameter in electronic portable system design where excess power dissipation can lead to expensive and less reliable systems. A system prototype has been developed on a FPGA-based platform (including microprocessor modules). This FPGA-based prototype is currently being migrated to a SoC, which requires that the treatment of important issues such as clock handling, synthesis, testability and debugging is addressed.

关键词： Local area networks

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Fully-integrated WCDMA direct conversion SiGeC BiCMOS receiver

Fully-integrated WCDMA direct conversion SiGeC BiCMOS receiv...

引用

Bipolar/BiCMOS Circuits and technology Meeting

作者： P. Garcia B. Pellat J.-P. Blanc P. Persechini V. Knopik L. Baud F. Goussin D. Thevenet S. Majcherczak F. Reaute O. Richard P. Conti B. Szelag D. Belot Analog RF Design Group-CR&D STMicroelectronics Crolles France Advanced System Technology-39 ST Microelectronics N.V. Geneva Switzerland

This paper describes a WCDMA direct conversion receiver which has been integrated in a BiCMOS SiGe-carbon process featuring 0.25 /spl mu/m/f/sub T/=60 GHz bipolar transistors. This receiver includes an integrated RF-front-end with local oscillator quadrature generator, 5/sup th/ order Butterworth analog baseband lowpass filter (LPF) and variable gain amplifier (VGA), cut-off frequency calibrator, DAC for DC-offset calibration, serial bus interface and voltage and current reference generators. In the high/low gain modes, this device consumes 25 mA and 20 mA respectively with 2.7 V power supply. The die is wire bonded directly on the validation board. Within the receive band, the measurements show 51 dB of overall gain, NF=5 dB, IIP3= -9 dBm, ICP1 = -15dBm.

关键词： Multiaccess communication BiCMOS integrated circuits Gain Bipolar transistors Local oscillators Baseband Filters Cutoff frequency Calibration Voltage-controlled oscillators

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A Noise Reduction Filter For Full-Frame Data Imaging Devices

A Noise Reduction Filter For Full-Frame Data Imaging Devices

引用

作者： Bosco, Angelo Findlater, Keith Battiato, Sebastiano Castorina, Alfio STMicroeleotronics Imaging Group Advanced System Technology Lab Catania Italy STMicroelectronics Imaging Division Edinburgh United Kingdom

A noise reduction filter for full-frame data imaging devices was discussed. Fixed Pattern Noise and Temporal Noise are removed by analyzing a series of lines placed at the top of the imager. It allows to perform noise... 详细信息

关键词： Imaging techniques

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