This paper proposes an analytical study and a bit-error-rate (BER) analysis for antenna verification algorithm to be used in closed loop mode one antenna diversity. The purpose of such algorithm, envisaged in 3GPP, is...
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This paper proposes an analytical study and a bit-error-rate (BER) analysis for antenna verification algorithm to be used in closed loop mode one antenna diversity. The purpose of such algorithm, envisaged in 3GPP, is to improve the receiver performance in the case when the BTS applies a wrong phase rotation to antenna 2 because of a demodulation error on the reverse-link. After a deep analytical description of this algorithm, a performance analysis is done for comparing closed loop mode one scheme among the perfect-feedback case (uplink BER=0) and the case when the uplink is affected by a certain error rate, with and without antenna diversity.
Industry requires new advanced tools and methodologies for the design of complex system-on-chip platforms. In stmicroelectronics we developed an innovative retargetable technology for the analysis and optimization of ...
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Industry requires new advanced tools and methodologies for the design of complex system-on-chip platforms. In stmicroelectronics we developed an innovative retargetable technology for the analysis and optimization of embedded software. In this paper we provide an overview of our retargetable tool chain which consists of: a specification reader a disassembler a code analyzer and a functional simulator. Their capabilities, specific features and limitations are described in detail.
With the projected explosion of low-cost bandwidth availability, the intensive processing tasks and service hosting will move close to consumers on the "intelligent edge" of the network, where a significant ...
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ISBN:
(纸本)0769509932
With the projected explosion of low-cost bandwidth availability, the intensive processing tasks and service hosting will move close to consumers on the "intelligent edge" of the network, where a significant portion of the future storage, processing and network management will take place. We address the rationale for this change, the characteristics of the network processor architecture required to address it, and the software development tools needed in order to improve time-to-market without sacrificing embedded software performance.
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